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APA150 Datasheet(PDF) 68 Page - Microsemi Corporation |
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APA150 Datasheet(HTML) 68 Page - Microsemi Corporation |
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68 / 178 page  ProASICPLUS Flash Family FPGAs 2- 58 v5.9 Asynchronous SRAM Read, Address Controlled, RDB=0 Asynchronous SRAM Read, RDB Controlled Note: The plot shows the normal operation status. Figure 2-31 • Asynchronous SRAM Read, Address Controlled, RDB = 0 Table 2-55 • TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/Industrial TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883B Symbol txxx Description Min. Max. Units Notes ACYC Read cycle time 7.5 ns OAA New DO access from RADDR stable 7.5 ns OAH Old DO hold from RADDR stable 3.0 ns RPAA New RPE access from RADDR stable 10.0 ns RPAH Old RPE hold from RADDR stable 3.0 ns Note: The plot shows the normal operation status. Figure 2-32 • Asynchronous SRAM Read, RDB Controlled RPE DO RADDR tOAH tRPAH tOAA tRPAA tACYC RB=(RDB+RBLKB) RPE DO tORDH tORDA tRPRDA tRDML tRDCYC tRDMH tRPRDH |
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