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AD7302 Datasheet(PDF) 13 Page - Analog Devices |
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AD7302 Datasheet(HTML) 13 Page - Analog Devices |
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13 / 16 page ![]() AD7302 –13– REV. 0 APPLICATIONS Bipolar Operation Using the AD7302 The AD7302 has been designed for single supply operation, but bipolar operation is achievable using the circuit shown in Figure 32. The circuit shown has been configured to achieve an output voltage range of –5 V < VO < +5 V. Rail-to-rail operation at the amplifier output is achievable using an AD820 or OP295 as the output amplifier. The output voltage for any input code can be calculated as follows: VO = [(1+R4/R3) × (R2/(R1+R2) × (2 × V REF × D/256)] – R4 × V REF/R3 where D is the decimal equivalent of the code loaded to the DAC and VREF is the reference voltage input. With VREF = 2.5 V, R1 = R3 = 10 k Ω and R2 = R4 = 20 kΩ and VDD = 5 V. VOUT = (10 × D/256) – 5 V AD7302 VOUTA 10µF 0.1µF VDD = 5V VDD AGND AD780/REF192 WITH VDD = 5V OR AD589 WITH VDD = 3V REF IN GND VOUT VIN 0.1µF EXT REF R1 10k Ω R2 20k Ω R4 20k Ω R3 10k Ω +5V –5V ±5V DGND AD820/ OP295 Figure 32. Bipolar Operation Using the AD7302 Decoding Multiple AD7302 in a System The CS pin on the AD7302 can be used in applications to decode a number of DACs. In this application all DACs in the system receive the same input data, but only the CS to one of the DACs will be active at any one time allowing access to two channels in the system. The 74HC139 is used as a two-to-four line decoder to address any of the DACs in the system. To prevent timing errors from occurring, the enable input should be brought to its inactive state while the coded address inputs are changing state. Figure 33 shows a diagram of a typical setup for decoding multiple AD7302 devices in a system. The built-in power-on reset circuit on the AD7302 ensures that the outputs of all DACs in the system power up with zero volts on their outputs. AD7302 D0 D8 VOUTA VOUTB ENABLE 74HC139 DATA BUS DGND CODED ADDRESS 1A 1B 1Y0 1Y1 1Y2 1Y3 VCC VDD 1 AD7302 D0 D8 VOUTA VOUTB AD7302 D0 D8 VOUTA VOUTB AD7302 D0 D8 VOUTA VOUTB Figure 33. Decoding Multiple AD7302 DACs in a System AD7302 As a Digitally Programmable Window Detector A digitally programmable upper/lower limit detector using the two DACs in the AD7302 is shown in Figure 34. The upper and lower limits for the test are loaded to DACs A and B, which in turn set the limits on the CMP04. If a signal at the VIN input is not within the programmed window an LED will indicate the fail condition. AD7302 VDD +5V VOUTA DGND REFIN VIN PASS/FAIL 1/2 CMP04 1/6 74HC05 FAIL PASS 1k 0.1µF 10µF WR CS A/B 1k VOUTB LDAC CLR DVDD PD AGND D0 D7 Figure 34. Programmable Window Detector |
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