–13–

REV. A

AD7898

SCLK

THREE-STATE

CS

SDATA

1

16

11

234

Figure 11. Entering Power-Down when in Mode 1

SCLK

CS

SDATA

111

16

16

1

THE PART BEGINS

TO POWER UP

THE PART IS FULLY

POWERED UP

INVALID DATA

VALID DATA

Figure 12. Exiting Power-Down when in Mode 1

To enter power-down, the conversion process must be inter-

rupted by bringing

CS high anywhere after the fourth falling

edge of SCLK and before the 11th falling edge of SCLK as

shown in Figure 11. Once

CS has been brought high in this

window of SCLK, then the part will enter power-down and the

conversion that was initiated by the falling edge of

CS will be

terminated and SDATA will go back into three-state.

In order to exit this mode of operation and power the AD7898

up again, a dummy conversion is performed. On the falling edge

of

CS the device will begin to power up, and will continue to

power up as long as

CS is held low until after the falling edge of

the 11th SCLK. The device will be fully powered up once 16

SCLKs have elapsed and valid data will result from the next

conversion as shown in Figure 12. If

CS is brought high before

the 11th falling edge of SCLK, the AD7898 will go back into

power-down. This avoids accidental power-up due to glitches

on the

CS line or an inadvertent burst of eight SCLK cycles

while

CS is low. So although the device may begin to power up

on the falling edge of

CS, it will power down again on the rising

edge of

CS as long as it occurs before the 11th SCLK falling edge.

Power-Up Times

The power-up time of the AD7898 is typically 4.33

µs, which

means that with any frequency of SCLK up to 3.7 MHz, one

dummy cycle will always be sufficient to allow the device to

power up. Once the dummy cycle is complete, the ADC will be

fully powered up and the input signal will be properly acquired.

which the bus goes back into three-state after the dummy con-

version, to the next falling

CS edge.

When powering up from power-down mode at any SCLK fre-

quency a dummy cycle is sufficient to power up the device and

cycle of 16 SCLKs must always elapse to power up the device

µs would be sufficient to power up

frequency was applied to the ADC, the cycle time would be 16

µs.

In one dummy cycle, 16

µs, the part would be powered up and

µs with a 1 MHz SCLK

just over four SCLK cycles would have elapsed. At this stage the

ADC would be fully powered up and the signal acquired. So, in

this case,

CS could be brought high after the 11th SCLK falling

MICROPROCESSOR/MICROCONTROLLER INTERFACE

FOR MODE 0 OPERATION

The AD7898 provides a 3-wire serial interface that can be

used for connection to the serial ports of DSP processors and

microcontrollers. Figures 13 through 16 show the AD7898

interfaced to a number of different microcontrollers and DSP

processors. The AD7898 accepts an external serial clock and,

as a result, in all interfaces shown here, the processor/controller

is configured as the master, providing the serial clock with the

AD7898 configured as the slave in the system. The AD7898 has

no BUSY signal, therefore a read operation should be timed to

occur 3.3

µs after CONVST goes low.

8x51/L51 to AD7898 Interface

Figure 13 shows an interface between the AD7898 and the

8x51/L51 microcontroller. The 8x51/L51 is configured for its

Mode 0 serial interface mode. The diagram shows the simplest

form of the interface where the AD7898 is the only part con-

nected to the serial port of the 8x51/L51 and, therefore, no

decoding of the serial read operations is required.

AD7898

SDATA

P3.0

8x51/L51

SCLK

P3.1

Figure 13. 8x51/L51 to AD7898 Interface