MPQ4470GL datasheet(13/20 Pages) MPS

13 / 20 page

MPQ4470/4470A–HIGH-EFFICIENCY, FAST-TRANSIENT, SYNCHRONOUS, STEP-DOWN CONVERTER, AEC-Q100 QUALIFIED

MPQ4470/4470A Rev. 1.1

www.MonolithicPower.com

8/26/2013

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

Figure 7 shows an equivalent circuit in PWM

mode with the HS-FET OFF and without an

external ramp circuit. The ESR ripple dominates

the output ripple. The VFB downward slope is:

REF

SLOPE1

ESR V

−×

(7)

From equation 7, the VFB downward slope is

proportional to ESR/L. Therefore, it’s necessary

to know the minimum ESR value of the output

capacitors without an external ramp. There is

also an inductance limit: A smaller inductance

leads to more stability. Based on bench

experiments, keep VSLOPE1 around 15V/ms to

30V/ms.

In skip mode, the external ramp does not affect

the downward slope, and VFB ripple’s downward

slope is the same with or without the external

ramp. Figure 8 shows an equivalent circuit with

the HS-FET off and the current modulator

regulating the LS-FET.

IMOD

Figure 8: Simplified Circuit in Skip Mode

The VFB ripple’s downward slope is:

()

−

+×

REF

SLOPE2

OUT

(8)

To keep the system stable during light loads,

avoid large VFB resistors. Also, keep the VSLOPE2

value around 0.4V/ms to 0.8mV/ms. Note that

IMOD is excluded from the equation because it

does not impact the system’s light-load stability.

Soft-Start

The MPQ4470/4470A employs soft start (SS) to

ensure a smooth output during power-up. When

the EN pin goes HIGH, an internal current source

(8.5μA) charges up the SS capacitor (CSS). The

CSS voltage takes over the REF voltage to the

PWM comparator. The output voltage smoothly

ramps up with VSS. Once VSS reaches the same

level as VREF, it continues ramping up while VREF

takes over the PWM comparator. At this point,

soft-start finishes and the MPQ4470/4470A

enters steady-state.

CSS is then:

()

( )

()

REF

tms

CnF

×μ

(9)

If the output capacitors have large capacitance

values, avoid setting a short SS or risk hitting the

current limit during SS. Select a minimum value

of 4.7nF if the output capacitance value exceeds

330μF.

Power Good (PGOOD)

The MPQ4470/4470A has power-good (PGOOD)

output. The PGOOD pin is the open drain of a

MOSFET. It should connect to VCC or some other

voltage source through a resistor (e.g. 100kΩ). In

the presence of an input voltage, the MOSFET

turns ON so that the PGOOD pin is pulled to

GND before SS is ready. After VFB reaches

90%×VREF, the PGOOD pin is pulled HIGH after a

delay; typically 700μs.

When the FB voltage drops to 85%×VREF, the

PGOOD pin is pulled LOW.

Over-Current Protection (OCP) and Short-

Circuit Protection (SCP)

The MPQ4470/4470A has cycle-by-cycle over-

current limit control. The inductor current is

monitored during the ON state. Once the inductor

current exceeds the current limit, the HS-FET

turns OFF. At the same time, the OCP timer

starts. The OCP timer is set at 100μs. Hitting the

current limit during each cycle during this 100μs

time frame will trigger hiccup SCP.

If a short circuit occurs, the MPQ4470/4470A will

immediately hit its current limit and VFB will drop

below 50%×VREF (0.815V). The device considers

this an output dead short and will trigger hiccup

SCP immediately.

Over/Under-Voltage Protection (OVP/UVP)

The MPQ4470 monitors the output voltage

through the tap of a resistor divider to the FB pin

to detect output over-voltage conditions. A VFB

that exceeds 125%×VREF (0.815V) triggers OVP

latch-off. Once OVP triggers, the LS-FET turns

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