AD9203ARURL7 datasheet(16/28 Pages) AD

16 / 28 page

AD9203

Rev. B | Page 16 of 28

–40

–50

–60

–70

–80

–90

40.0

42.5

45.0

47.5

50.0

52.5

55.0

57.5

60.0

DUTY CYCLE (%)

THD

SNR

Figure 31. THD and SNR vs. Clock Duty Cycle

(fIN = 5 MHz Differential, Clock = 40 MSPS)

Table 5. Power Programming Resistance

Clock MSPS

Resistor Value (k)

5 to 10

100

15 to 20

200

>20

500

POWER CONTROL

Power consumed by the AD9203 may be reduced by placing a

resistor between the PWRCON pin and ground. This function

will be valuable to users who do not need the AD9203’s high

conversion rate, but do need even lower power consumption.

The external resistor sets the programming of the analog

current mirrors. Table 5 illustrates the relationship between

programmed power and performance.

At lower clock rates, less power is required within the analog

sections of the AD9203. Placing an external resistor on the

PWRCON pin will shunt control current away from some of the

current mirrors. This enables the ADC to convert low data rates

with extremely low power consumption.

INTERFACING TO 5 V SYSTEMS

The AD9203 can be integrated into 5 V systems. This is

accomplished by deriving a 3 V power supply from the existing

5 V analog power line through an AD3307-3 linear regulator.

Care must be maintained so that logic inputs do not exceed the

maximum rated values listed on the Specifications page.

CLOCK INPUT AND CONSIDERATIONS

The AD9203 internal timing uses the two edges of the clock

input to generate a variety of internal timing signals. Sampling

occurs on the falling edge. The clock input to the AD9203

operating at 40 MSPS may have a duty cycle between 45% to

55% to meet this timing requirement since the minimum

specified tCH and tCL is 11.25 ns. For clock rates below 40 MSPS,

the duty cycle may deviate from this range to the extent that

both tCH and tCL are satisfied. See Figure 31 for dynamics vs.

duty cycle.

High-speed, high-resolution A/Ds are sensitive to the quality of

the clock input. The degradation in SNR at a given full-scale

input frequency (fIN) due only to aperture jitter (tA) can be

calculated with the following equation:

SNR degradation = 20 log10 [1/2π fIN tA]

In the equation, the rms aperture jitter, tA, represents the

rootsum square of all the jitter sources, which include the clock

input, analog input signal, and A/D aperture jitter specification.

Undersampling applications are particularly sensitive to jitter.

Clock input should be treated as an analog signal in cases where

aperture jitter may affect the dynamic range of the AD9203.

Power supplies for clock drivers should be separated from the

A/D output driver supplies to avoid modulating the clock signal

with digital noise. Low jitter crystal controlled oscillators make

the best clock sources. If the clock is generated from another

type of source (by gating, dividing or another method), it

should be retimed by the original clock at the last step.

The clock input is referred to the analog supply. Its logic

threshold is AVDD/2.

DIGITAL INPUTS AND OUTPUTS

Each of the AD9203 digital control inputs, 3-STATE, DFS, and

STBY are referenced to analog ground. CLK is also referenced

to analog ground. A low power mode feature is provided such

that for STBY = HIGH and the static power of the AD9203

drops to 0.65 mW.

Asserting the DFS pin high will invert the MSB pin, changing

the data to a twos complement format.

The AD9203 has an OTR (out of range) function. If the input

voltage is above or below full scale by 1 LSB, the OTR flag will

go high. See Figure 32.

AD9203ARURL7 Datasheet(PDF) 16 Page - Analog Devices

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