REV.

B

–16–

AD9845B

Table IV. Clamp Level Register Contents (Default Value x080)

MSB

LSB

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Clamp Level (LSB)

X

XX

0000

0

000

0

0000

0

001

1

0000

0

010

2

∑∑

∑∑

∑∑

11111110

254

11111111

255

Table V. Control Register Contents (Default Value x000)

Data Out

DATACLK

CLP/PBLK

SHP/SHD

PxGA

Color Steering Modes

D10 D9

D8 D7

D6

D5

D4

D3

2

D2 D1 D0

X0 Enable

0Rising Edge Trigger

0 Active Low 0 Active Low

0 Disable 0

0

0

Steering Disabled

1 Three-State

1 Falling Edge Trigger 1 Active High 1 Active High

1 Enable

0

0

1

Mosaic Separate

010

Interlace

011

3-Color

100

4-Color

101

VD Selected

110

Mosaic Repeat

111

User Specified

NOTES

Table VI. PxGA Gain Registers for Gain0, Gain1, Gain2, Gain3 (Default Value x000)

MSB

LSB

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Gain (dB)

*

XXXXX

011111+9.5

∑∑

∑∑

∑∑

000000+3.5

111111+3.3

∑∑

∑∑

∑∑

100000

–2.5

*Control Register Bit D3 must be set high (PxGA Enable) to use the PxGA Gain Registers.