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AD9874EB Datasheet(PDF) 11 Page - Analog Devices

Part # AD9874EB
Description  IF Digitizing Subsystem
PDF  40 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9874EB Datasheet(HTML) 11 Page - Analog Devices

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REV. A
AD9874
–11–
CHANNEL BANDWIDTH – kHz
10.0
10
7.5
1000
100
9.5
9.0
8.5
8.0
24-BIT
I/Q DATA
16-BIT
I/Q DATA
16-BIT
I/Q DATA
w/ DVGA
ENABLED
TPC 10a. Noise Figure vs. BW (Mini-
mum Attenuation, fCLK = 13 MSPS)
VGA ATTENUATION – dB
11.5
0
7.0
12
6
9
3
11.0
10.5
10.0
9.5
9.0
8.5
8.0
7.5
BW = 6.78kHz
(K = 0, M = 15)
BW = 12.04kHz
(K = 0, M = 8)
BW = 27.08kHz
(K = 0, M = 3)
TPC 11a. Noise Figure vs. VGA
Attenuation (fCLK = 13 MSPS)
IFIN – dBm
–45
–130
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–42
–39
–36
–33
–30
–27
–24
LOW BIAS
PIN
HIGH BIAS
–5
–30
–10
–15
–20
–25
–40
–35
–45
TPC 12a. IMD vs. IFIN (fCLK = 13 MSPS)
CHANNEL BANDWIDTH – kHz
10.0
10
7.5
1000
100
9.5
9.0
8.5
8.0
24-BIT
DATA
16-BIT
DATA
16-BIT DATA
w/ DVGA
ENABLED
TPC 10b. Noise Figure vs. BW (Mini-
mum Attenuation, fCLK = 18 MSPS)
VGA ATTENUATION – dB
14
0
7
12
6
9
3
13
12
11
10
9
8
BW = 15kHz
(K = 0, M = 9)
BW = 50kHz
(K = 0, M = 2)
BW = 75kHz
(K = 0, M = 1)
TPC 11b. Noise Figure vs. VGA
Attenuation (fCLK = 18 MSPS)
IFIN – dBm
–45
–130
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–42
–39
–36
–33
–30
–27
–24
LOW BIAS
PIN
HIGH BIAS
–5
–30
–10
–15
–20
–25
–40
–35
–45
TPC 12b. IMD vs. IFIN (fCLK = 18 MSPS)
CHANNEL BANDWIDTH – kHz
10.0
10
7.5
1000
100
9.5
9.0
8.5
8.0
24-BIT
DATA
16-BIT
DATA
16-BIT DATA
w/ DVGA
ENABLED
TPC 10c. Noise Figure vs. BW (Mini-
mum Attenuation, fCLK = 26 MSPS)
VGA ATTENUATION – dB
14
0
7
12
6
9
3
13
12
11
10
9
8
BW = 27.08kHz
(K = 1, M = 9)
BW = 90.28kHz
(K = 1, M = 2)
BW = 135.42kHz
(K = 1, M = 1)
TPC 11c. Noise Figure vs. VGA
Attenuation (fCLK = 26 MSPS)
IFIN – dBm
–45
–130
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–42
–39
–36
–33
–30
–27
–24
LOW BIAS
PIN
HIGH BIAS
–5
–30
–10
–15
–20
–25
–40
–35
–45
TPC 12c. IMD vs. IFIN (fCLK = 26 MSPS)
(VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = VDDx, VDDQ = VDDP = 5.0 V,
fCLK = 18 MSPS, fIF = 109.56 MHz, fLO = 107.4 MHz,
TA = 25 C, LO = –5 dBm, LO and CLK Synthesizer Disabled, 16-Bit Data with AGC and DVGA enabled, unless otherwise noted.)
1
1Data taken with Toko FSLM series 10
µH inductors.
2High Bias corresponds to LNA_Mixer Setting of 33 in SPI Register 0x01.
3Low Bias corresponds to LNA_Mixer Setting of 12 in SPI Register 0x01.



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