AM53CF96 datasheet(34/76 Pages) AMD

34 / 76 page

P R E L I M I N A R Y

AMD

Am53CF94/Am53CF96

CNTLREG3

FASTSCSI

FASTCLK

Clock

Mode of

Bit 4

Bit 3

Frequency

Operation

25–40 MHz

10 MBytes/

sec,

Fast SCSI

25–40 MHz

5 MBytes/sec,

SCSI-1

––

< = 25 MHz

5 MBytes/sec,

SCSI-1

–– = don’t care

CNTLREG3 – Bit 2 – LBTM – Last Byte Transfer

Mode

The LBTM bit specifies how the last byte in an odd byte

transfer is handled during 16-bit DMA transfers (modes

1, 2, 3). This mode is not used if byte control is selected

via BUSMD 1:0 = 10 and SBO (Select Byte Order) bit in

the CNTLREG2is set to ‘1’. This mode has no affect dur-

ing 8-bit DMA transfers (mode 0) and on transfers on the

SCSI bus.

When the LBTM bit is set the DREQ signal will not be

asserted for the last byte, instead the host will read or

write the last byte from or to the FIFO. When the LBTM

bit is reset the DREQ signal will be asserted for the last

byte and the following 16-bit DMA transfer will contain

the last byte on the lower bus. While the upper bus

(DMA 15:8/DMAP 1) will be all ones.

The LBTM bit is reset by hard or soft reset.

CNTLREG3 – Bit 1 – MDM – Modify DMA Mode

The MDM bit is used to modify the timing of the

DACK

signal with respect to the

DMARD and DMAWR signals.

The MDM bit is used in conjunction with the Burst Size 8

(BS8) bit in the CNTLREG3. Both bits have to be set for

proper operation.

When the MDM bit is set and the device is in a DMA read

or write mode the

DACK signal will remain asserted

while the data is strobed by the

DMARD or DMAWR sig-

nals. In the DMA read mode when BUSMD 1:0 = 11 the

DACK signal will toggle for every DMA read.

When the MDM bit is reset and the device is in a DMA

read or write mode the

DACK signal will toggle every

time the data is strobed by the

DMARD or DMAWR

signals.

CNTLREG3 – Bit 0 – BS8 – Burst Size 8

The BS8 bit is used to modify the timing of the DREQ

signal with respect to the

DMARD and DMAWR signals.

The BS8 bit is used in conjunction with the Modify DMA

Mode (MDM) bit in the CNTLREG3. Both bits have to be

set for proper operation.

When the BS8 bit is set the device delays the assertion

of the DREQ signal until 8 bytes or 4 words transfer is

possible.

When the BS8 bit is set and the device is in a DMA write

mode the DREQ signal will be asserted only when 8 byte

locations are available for writing. In the DMA read

mode the DREQ signal will go active under the following

circumstances:

At the end of a transfer,

In the Target mode,

– when the transfer is complete

– when the

ATN signal is active

In the Initiator mode,

– when the Current Transfer Register (CTCREG)

is decremented to zero

– after any phase change

In the middle of a transfer

In the Initiator mode,

– when the last 8 bytes of the FIFO are full

– during Synchronous Data-In transfer when the

Event Transfer Count Register is greater than

7 and the last 8 bytes of the FIFO are full.

When the BS8 bit is reset and the device is in a DMA

read or write mode the DREQ signal will toggle every

time the data is strobed by the

DMARD or DMAWR

signals.

Using (Bit 0 (BS8) and Bit 1 (MDM) of Control

ent combination modes shown in the table below.

Maximum

(MDM)

(BS8)

Function

Synchronous

Bit 1

Bit 0

Offset

Normal DMA Mode

Burst Size 8 Mode

Reserved

–

Modified DMA Mode

AM53CF96 Datasheet(PDF) 34 Page - Advanced Micro Devices

AM53CF96 Datasheet(HTML) 34 Page - Advanced Micro Devices

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