AM79C873KCW datasheet(12/44 Pages) AMD

12 / 44 page

Am79C873

PRELIMINARY

FUNCTIONAL DESCRIPTION

The NetPHY-1 Fast Ethernet single-chip transceiver,

provides the functionality as speciﬁed in the IEEE

802.3u standard, integrates complete 100BASE-FX,

100BASE-TX modules and a complete 10BASE-T

module. The NetPHY-1 device provides a Media Inde-

pendent Interface (MII) as deﬁned in the IEEE 802.3u

standard (Clause 22).

The NetPHY-1 device performs all Physical Coding

Sublayer (PCS), Physical Media Access (PMA),

Twisted Pair Physical Medium Dependent (TP-PMD)

sublayer, 10BASE-T Encoder/Decoder, and Twisted

Pair Media Access Unit (TPMAU) functions. Figure 1

shows the major functional blocks implemented in the

NetPHY-1 device.

Figure 1.

Functional Block Diagram

MII Interface

The purpose of the MII interface is to provide a simple,

easy to implement connection between the MAC Rec-

onciliation layer and the PHY. The MII is designed to

make the differences between various media transpar-

ent to the MAC sublayer.

The MII consists of a nibble wide receive data bus, a

nibble wide transmit data bus, and control signals to fa-

cilitate data transfers between the PHY and the Recon-

ciliation layer.

s TXD (transmit data) is a nibble (4 bits) of data that

are driven by the reconciliation sublayer synchro-

nously with respect to TX_CLK. For each TX_CLK

period which TX_EN is asserted, TXD (3:0) are ac-

cepted for transmission by the PHY.

s TX_CLK (transmit clock) output to the MAC recon-

ciliation sublayer is a continuous clock that provides

the timing reference for the transfer of the TX_EN,

TXD, and TX_ER signals.

s TX_EN (transmit enable) input from the MAC recon-

ciliation sublayer to indicate nibbles are being

pre-

sented on the MII for transmission on the physical

medium. TX_ER (transmit coding error) transitions

synchronously with respect to TX_CLK. If TX_ER is

asserted for one or more clock periods, and TX_EN

is asserted, the PHY will emit one or more symbols

that are not part of the valid data delimiter set some-

where in the frame being transmitted.

s RXD (receive data) is a nibble (4 bits) of data that

are sampled by the reconciliation sublayer syn-

chronously with respect to RX_CLK. For each

RX_CLK period which RX_DV is asserted, RXD

(3:0) are transferred from the PHY to the MAC

reconciliation sublayer.

s RX_CLK (receive clock) output to the MAC reconcil-

iation sublayer is a continuous clock that provides

the timing reference for the transfer of the RX_DV,

RXD, and RX_ER signals.

MII Interface

100Base

Receiver

10Base-T

Tranceiver

Carrier

Sense

Collision

Detection

Auto

Negotiation

MII Serial

Management

Interface

100Base

Transmitter

22164A-3

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