AM79C30AVC datasheet(15/101 Pages) AMD

15 / 101 page

Am79C30A/32A Data Sheet

Line Interface Unit (LIU)

The LIU connects to the four-wire S Interface through a

pair of isolation transformers, one for the transmit and

one for the receive direction, as shown in Figure 1.

The receiver section of the LIU consists of a differential

receiver, circuitry for bit timing recovery, circuitry for de-

tecting High and Low marks, and a frame recovery cir-

cuit for frame synchronization. The receiver converts

the received pseudo-ternary coded signals to binary

before delivering them to the other blocks of the

Am79C30A/32A. It also performs collision detection (E-

and D-bit comparison) per the CCITT recommenda-

tions so several TEs can be connected to the same S

Interface.

The transmitter consists of a binary to pseudo-ternary

encoder and a differential line driver which meets the

CCITT recommendations for the S Interface.

The Am79C30A/32A can establish multiframe synchro-

nization, receive S bits, and transmit Q bits synchro-

nized to the received frame.

External Interface

The LIU can be connected to both point-to-point and

point-to-multipoint configurations at the CCITT S refer-

ence point. The point-to-point configuration consists of

one TE connected to the NT or PABX linecard. The

DLC

D-channel Mode Register 1

DMR1

R/W

86H

One byte transferred

DLC

D-channel Mode Register 2

DMR2

R/W

87H

One byte transferred

DLC

—

Perform 1–7

—

88H

4 bytes loaded 1–7

DLC

D-channel Receive Byte Count

DRCR

89H

LSB, MSB

DLC

Random Number Generator

RNGR1 (LSB)

R/W

8AH

One byte transferred

DLC

Random Number Generator

RNGR2 (MSB)

R/W

8BH

One byte transferred

DLC

First Received Byte Address

FRAR4

R/W

8CH

One byte transferred

DLC

Second Received Byte Address

SRAR4

R/W

8DH

One byte transferred

DLC

D-channel Mode Register 3

DMR3

R/W

8EH

One byte transferred

DLC

D-channel Mode Register 4

DMR4

R/W

8FH

One byte transferred

DLC

—

Perform 12–15

—

90H

FRAR4, SRAR4, DMR3,

DMR4

DLC

Address Status Register

ASR

91H

One byte transferred

DLC

Extended FIFO Control Register

EFCR

R/W

92H

One byte transferred

Peripheral Port Control Register 1

PPCR1

R/W

C0H

One byte transferred

Peripheral Port Status Register

PPSR

C1H

One byte transferred

Peripheral Port Interrupt Enable

PPIER

R/W

C2H

One byte transferred

Monitor Transmit Data Register

MTDR

C3H

One byte transferred

Monitor Receive Data Register

MRDR

C3H

One byte transferred

C/I Transmit Data Register 0

CITDR0

C4H

One byte transferred

C/I Receive Data Register 0

CIRDR0

C4H

One byte transferred

C/I Transmit Data Register 1

CITDR1

C5H

One byte transferred

C/I Receive Data Register 1

CIRDR1

C5H

One byte transferred

Peripheral Port Control Register 2

PPCR2

R/W

C8H

One byte transferred

Peripheral Port Control Register 3

PPCR3

R/W

C9H

One byte transferred

Table 7.

Indirect Register Access Guide (Continued)

Operation

Block

Number

Indirect Name

Mode

Address

Byte Sequence

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