AM79C90JC datasheet(31/62 Pages) AMD

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P R E L I M I N A R Y

AMD

Am79C90

for this packet) it will transmit the current buffer and up-

date the status of current Ring with the BUFF and UFLO

error bits set. If the C-LANCE owns the 2nd DTE, it will

also read the buffer address and the buffer byte count of

this entry. Once the C-LANCE has finished emptying the

current buffer, it clears the OWN bit for this buffer, and

immediately starts loading the Transmit FIFO from the

next (2nd) buffer. Between DMA bursts, starting from

the 2nd buffer, the C-LANCE does a lookahead again to

check if it owns the next (3rd) buffer. This activity goes

on until the last transmit DTE indicates the end of the

packet (TMD1, ENP = 1). Once the last part of the pack-

et has been transmitted out from the Transmit FIFO to

the medium, the C-LANCE will update the status in

TMD1, TMD3 (TMD3 is updated only when there is an

error) and will relinquish the last buffer to the CPU. The

C-LANCE tries to own the next buffer (first buffer of the

next packet), immediately after it relinquishes the last

buffer of the current packet. This guarantees the back-

to-back transmission of the packets. If the C-LANCE

does not own the next buffer, it then polls the TX ring

every 1.6 ms.

When an error occurs before all of the buffers get trans-

mitted, the status, TMD3 , is updated in the current DTE,

own bit is cleared in TMD1, and TINT bit is set in CSR0

which causes an interrupt if INEA = 1. The C-LANCE will

then skip over the rest of the descriptors for this packet

(clears the OWN bit and sets the TINT bit in CSR0) until

it finds a buffer with both the STP and OWN bit being set

(this indicates the first buffer for the next packet).

When the transmit buffers are not data chained (current

descriptor’s ENP = 1), the C-LANCE will not perform any

lookahead operation. It will transmit the current buffer,

update the TMD3 if any error, and then update the

status and clear the OWN bit in TMD1 . The C-LANCE

will then immediately check the next descriptor in the

ring to see if it owns it. If it does, the C-LANCE will also

read the rest of the entries from the descriptor table. If

the C-LANCE does not own it, it will poll the ring once

every 1.6 ms until it owns it. User may set the TDMD bit

in CSR0 when it has relinquished a buffer to the

C-LANCE. This will force the C-LANCE to check the

OWN bit at this buffer without waiting for the polling time

to elapse.

Receive Ring Buffer Management

Receive Ring access is similar to the transmit ring ac-

cess. Once the receiver is enabled, the C-LANCE will al-

ways try to have a receive buffer available, should there

be a packet addressed to this node for reception. There-

fore, when the C-LANCE is idle, it will poll the receive

ring entry once every 1.6 ms, until it owns the current re-

ceive DTE. Once the C-LANCE owns the buffer, it will

read RMD0 and RMD2 to get the rest of buffer address

and buffer byte count. When a packet arrives from the

physical medium, after the Address Recognition Logic

accepts the packet, the C-LANCE will immediately poll

the Receiver Ring once for a buffer. If it still does not own

the buffer, it will set the MISS error in CSR0 and will not

poll the receive ring until the packet ends.

Assuming the C-LANCE owns a receive buffer when the

packet arrives, it will perform a lookahead operation on

the next DTE between periods when it is dumping the re-

ceived data from the Receive FIFO to the first receive

buffer in case the current buffer requires data chaining.

When the C-LANCE owns the buffer, the lookahead op-

eration consists of three separate single word DMA

reads: RMD1, RMD0, and RMD2. When the C-LANCE

does not own the next buffer, the lookahead operation

consists of only one single DMA read, RMD1. Either

lookahead operation is done only once. Following the

lookahead operation, whether C-LANCE owns the next

buffer or not, the C-LANCE will transfer the data from

Receive FIFO to the first receive buffer for this packet in

burst mode (8 word transfer per one DMA cycle

arbitration).

If the packet being received requires data chaining, and

the C-LANCE does not own the second DTE, the

C-LANCE will update the current buffer status, RMD1,

with the BUFF and/or OFLO error bits set. If the

C-LANCE does own the next buffer (second DTE) from

previous lookahead, the C-LANCE will relinquish the

current buffer and start filling up the second buffer for

this packet. Between the time that the C-LANCE is

transferring data from the Receive FIFO to the second

buffer, it does a lookahead operation again to see if it

owns the next (third) buffer. If the C-LANCE does own

the third DTE, it will also read RMD0, and RMD2 to get

the rest of buffer pointer address and buffer byte count.

This activity continues on until the C-LANCE recognizes

the end of the packet (physical medium is idle); it then

updates the current buffer status with the end of packet

bit (ENP) set. The C-LANCE will also update the mes-

sage byte count (RMD3) with the total number of bytes

received for this packet in the current buffer (the last

buffer for this packet).

The dual FIFOs in the C-LANCE are utilized by the inter-

nal microcode to guarantee that continuous receive ac-

tivity does not prevent the servicing of pending transmit

packets. The microcode includes a single transmit de-

scriptor poll operation at the beginning of buffer DMA

operations for an incoming receive packet. This single

transmit descriptor poll is performed only once during

the receive microcode routine for each packet that is re-

ceived. If the OWN bit in the transmit descriptor is set,

burst transfers to the Transmit FIFO are interleaved with

burst transfers from the Receive FIFO. By interleaving

the transmit buffer transfers with the receive buffer

transfers, the beginning of the transmit packet is

preloaded in the Transmit FIFO, ready to be transmitted

immediately following the end of the receive packet on

the wire.

AM79C90JC Datasheet(PDF) 31 Page - Advanced Micro Devices

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