AM79C90PCTR datasheet(8/62 Pages) AMD

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AMD

P R E L I M I N A R Y

Am79C90

FUNCTIONAL DESCRIPTION

The parallel interface of the CMOS Local Area Network

Controller for Ethernet (C-LANCE) has been designed

to be “friendly” or easy to interface to a variety of popular

microprocessors. These microprocessors include the

Am29000, 80x86, 680x0, Z8000 and LSI-11. The

C-LANCE has a 24-bit wide linear address space when

it is in the Bus Master Mode. A programmable mode of

operation allows byte addressing in one of two ways:

a Byte/Word control signal compatible with the 80x86

and Z8000 or an Upper Data Strobe and Lower Data

Strobe signal compatible with microprocessors such as

the 68000. A programmable polarity on the Address

Strobe signal eliminates the need for external logic. The

C-LANCE interfaces with both multiplexed and de-

multiplexed data busses and features control signals for

address/data bus transceivers. The C-LANCE is pin-for-

pin compatible with AMD’s LANCE device (Am7990).

Please refer to Appendix B for a complete comparison

between the C-LANCE and LANCE devices.

A16–A23

DAL0–DAL15

CPU

ALE

Buffer

Data and

Address

Bits 0–15

Address

Bits

16–23

Control

Decoder

Buffer

Latch

DAL0–DAL15 A16–A23 Control

ALE

A16–A23

C-LANCE

ALE

ADR

DAL0 – DAL15

A16–A23

17881B-5

Figure 1. C-LANCE/CPU Interfacing Multiplexed Bus

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