AM79C90JCTR datasheet(22/62 Pages) AMD

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P R E L I M I N A R Y

Am79C90

Bit

Name

Description

TDMD

TRANSMIT DEMAND, when set,

causes the C-LANCE to access the

Transmit Descriptor Ring without

waiting for the polltime interval to

elapse. TDMD need not be set to

transmit a packet; it merely hastens

the C-LANCE’s response to a Trans-

mit Descriptor Ring entry insertion by

the host.

TDMD is WRITE WITH ONE ONLY

and is cleared by the microcode after

it is used. It may read as a “1” for a

short time after it is written because

the microcode may have been busy

when TDMD was set. It is also

cleared by

RESET or by setting the

STOP bit. Writing a “0” in this bit has

no effect.

STOP

STOP disables the C-LANCE from

all external activity when set and

clears the internal logic. Setting

STOP is the equivalent of asserting

RESET. The C-LANCE remains in-

active and STOP remains set until

the STRT or INIT bit is set. If STRT,

INIT and STOP are all set together,

STOP will override the other bits and

only STOP will be set.

STOP is READ/WRITE WITH ONE

ONLY and set by RESET. Writing a

“0” to this bit has no effect. STOP is

cleared by setting either INIT or

STRT. CSR

3 must be reloaded

when the STOP bit is set.

STRT

START enables the C-LANCE to

send and receive packets, perform

direct memory access, and do buffer

management. The STOP bit must be

set prior to setting the STRT bit. Set-

ting STRT clears the STOP bit.

STRT is READ/WRITE and is set

with one only. Writing a “0” into this

bit has no effect. STRT is cleared by

RESET or by setting the STOP bit.

INIT

INITIALIZE, when set, causes the

C-LANCE to begin the initialization

procedure and access the Initializa-

tion Block. The STOP bit must be set

prior to setting the INIT bit. Setting

INIT clears the STOP bit.

INIT is READ/WRITE WITH “1”

ONLY. Writing a “0” into this bit has

no effect. INIT is cleared by

RESET

or by setting the STOP bit.

The C-LANCE latches CSR

0 during

a slave read; therefore, the CSR

status bits are guaranteed to be sta-

ble for the duration of the CSR

access.

Control and Status Register 1 (CSR1)

READ/WRITE:

Accessible only when the STOP bit

of CSR

0 is a ONE and RAP = 01.

The C-LANCE preserves the con-

tents of CSR

1 after STOP.

‘0’

1 0

IADR

(15:01)

17881B-16

Bit

Name

Description

15:01

IADR

The low order 15 bits of the address

of the first word (lowest address) in

the Initialization Block.

Must be zero.

Control and Status Register 2 (CSR2)

READ/WRITE:

Accessible only when the STOP bit

of CSR

0 is a ONE and RAP = 10.

The C-LANCE preserves the con-

tents of CSR

2 after STOP.

IADR (23:16)

17881B-17

RES

Bit

Name

Description

15:08

RES

Reserved. Read as zeroes. Write as

zeroes.

07:00

IADR

The high order 8 bits of the address

of the first word (lowest address) in

the initialization Block.

AM79C90JCTR Datasheet(PDF) 22 Page - Advanced Micro Devices

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