AM79C940VCW datasheet(36/122 Pages) AMD

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AMD

Am79C940

dium. An initial period shorter than 2/3 of the interval is

permissible including zero.”

The MAC engine implements the optional receive two

part deferral algorithm, with a first part inter-frame-

spacing time of 6.0

µs. The second part of the inter-

frame-spacing interval is therefore 3.6

µs.

The MACE device will perform the two part deferral al-

gorithm as specified in Section 4.2.8 (Process Defer-

ence). The Inter Packet Gap (IPG) timer will start timing

the 9.6

µs InterFrameSpacing after the receive carrier is

de-asserted. During the first part deferral (Inter-

FrameSpacingPart1–IFS1) the MACE device will defer

any pending transmit frame and respond to the receive

message. The IPG counter will be reset to zero continu-

ously until the carrier deasserts, at which point the IPG

counter will resume the 9.6

µs count once again. Once

the IFS1 period of 6.0

µs has elapsed, the MACE device

will begin timing the second part deferral (Inter-

FrameSpacingPart2–IFS2) of 3.6

µs. Once IFS1 has

completed, and IFS2 has commenced, the MACE chip

will not defer to a receive packet if a transmit packet is

pending. This means that the MACE device will not at-

tempt to receive an incoming packet, and it will start to

transmit at 9.6

µs regardless of network activity, forcing

a collision if an existing transmission is in progress. The

MACE device will guarantee to complete the preamble

(64-bit) and jam (32-bit) sequence before ceasing trans-

mission and invoking the random backoff algorithm.

In addition to the deferral after receive process, the

MACE device also allows transmit two part deferral to be

implemented as an option. The option can be disabled

using the DXMT2PD bit in the MAC Configuration Con-

trol register. Two part deferral after transmission is use-

ful for ensuring that severe IPG shrinkage cannot occur

in specific circumstances, causing a transmit message

to follow a receive message so closely, as to make them

indistinguishable.

During the time period immediately after a transmission

has been completed, the external transceiver (in the

case of a standard AUI connected device), should gen-

erate the SQE Test message (a nominal 10 MHz burst of

5-15 BT duration) on the CI

± pair (within 0.6–1.6 µs after

the transmission ceases). During the time period in

which the SQE Test message is expected the MACE de-

vice will not respond to receive carrier sense.

See ANSI/IEEE Std 802.3-1990 Edition,

7.2.4.6 (1)):

“At the conclusion of the output function, the

DTE opens a time window during which it ex-

pects to see the

signal_quality_error signal as-

serted on the Control In circuit. The time

window begins when the CARRIER_STATUS

becomes CARRIER_OFF. If execution of the

output function does not cause CARRIER_ON

to occur, no SQE test occurs in the DTE. The

duration of the window shall be at least 4.0

µs

but no more than 8.0

µs. During the time win-

dow the Carrier Sense Function is inhibited.”

The MACE device implements a carrier sense

blinding

period within 0

µs–4.0 µs from deassertion of carrier

sense after transmission. This effectively means that

when transmit two part deferral is enabled (DXMT2PD

in the MAC Configuration Control register is cleared) the

IFS1 time is from 4

µs to 6 µs after a transmission. How-

ever, since IPG shrinkage below 4

µs will not be encoun-

tered on correctly configured networks, and since the

fragment size will be larger than the 4

µs blinding win-

dow, then the IPG counter will be reset by a worst case

IPG shrinkage/fragment scenario and the MACE device

will defer its transmission. The MACE chip will not re-

start the carrier sense

blinding period if carrier is de-

tected within the 4.0–6.0

µs portion of IFS1, but will

restart timing of the entire IFS1 period.

Contention Resolution (Collision Handling)

Collision detection is performed and reported to the

MAC engine either by the integrated Manchester En-

coder/Decoder (MENDEC), or by use of an external

function (e.g. Serial Interface Adaptor, Am7992B) utiliz-

ing the GPSI.

If a collision is detected before the complete preamble/

SFD sequence has been transmitted, the MACE device

will complete the preamble/SFD before appending the

jam sequence. If a collision is detected after the pream-

ble/SFD has been completed, but prior to 512 bits being

transmitted, the MACE device will abort the transmis-

sion, and append the jam sequence immediately. The

jam sequence is a 32-bit all zeroes pattern.

The MACE device will attempt to transmit a frame a total

of 16 times (initial attempt plus 15 retries) due to normal

collisions (those within the slot time). Detection of colli-

sion will cause the transmission to be re-scheduled, de-

pendent on the backoff time that the MACE device

computes. Each collision which occurs during the trans-

mission process will cause the value of XMTRC in the

Transmit Retry Count register to be updated. If a single

retry was required, the ONE bit will be set in the Trans-

mit Frame Status. If more than one retry was required,

the MORE bit will be set, and the exact number of at-

tempts can be determined (XMTRC+1). If all 16 at-

tempts experienced collisions, the RTRY bit will be set

(ONE and MORE will be clear), and the transmit

message will be flushed from the XMTFIFO, either by

resetting the XMTFIFO (if no

End-of-Frame tag exists)

or by moving the XMTFIFO read pointer to the next free

location (If an End-of-Frame tag is present). If retries

have been disabled by setting the DRTRY bit, the MACE

device will abandon transmission of the frame on detec-

tion of the first collision. In this case, only the RTRY bit

AM79C940VCW Datasheet(PDF) 36 Page - Advanced Micro Devices

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