AM79C971VCW datasheet(131/265 Pages) AMD

131 / 265 page

Am79C971

131

10BASE-T receive polarity rever-

sal algorithm is disabled. Like-

wise,

when

DAPC = 0,

the

polarity reversal algorithm is en-

abled.

This bit only has meaning when

the 10BASE-T network interface

is selected.

Read/Write accessible only when

either the STOP or the SPND bit

is set.

MENDECL

MENDEC Loopback Mode. See

the description of the LOOP bit in

CSR15, bit 2.

Read/Write accessible only when

either the STOP or the SPND bit

is set.

LRT

(TMAU

mode)

Low

Receive

Threshold. When LRT = 1, the in-

ternal twisted pair receive thresh-

olds are reduced by 4.5 dB below

the standard 10BASE-T value

(approximately 3/5) and the un-

squelch threshold for the RXD

circuit will be 180 mV to 312 mV

peak.

When LRT = 0, the unsquelch

threshold for the RXD circuit will

be the standard 10BASE-T value,

300 mV to 520 mV peak.

In either case, the RXD circuit

post squelch threshold will be

one-half of the unsquelch thresh-

old.

This bit only has meaning when

the 10BASE-T network interface

is selected.

Read/Write accessible only when

either the STOP or the SPND bit

is set. Cleared by H_RESET or

S_RESET and is unaffected by

STOP.

TSEL

(AUI mode) Transmit Mode Se-

lect. TSEL controls the levels at

which the AUI drivers rest when

the AUI transmit port is idle.

When TSEL = 0, DO+ and DO-

yield “zero” differential to operate

transformer

coupled

loads

(Ethernet 2 and IEEE 802.3).

When TSEL = 1, the DO+ idles at

a higher value with respect to

DO-, yielding a logical HIGH state

(Ethernet 1).

This bit only has meaning when

the AUI network interface is se-

lected.

Read/Write accessible only when

either the STOP or the SPND bit

is set. Cleared by H_RESET or

S_RESET.

8-7

PORTSEL[1:0]Port Select bits allow for software

controlled selection of the net-

work medium. See Table 26.

PORTSEL

settings

AUI,

10BASE-T and MII are ignored

when the ASEL bit of BCR2 (bit 1)

has been set to 1.

Read/Write accessible only when

either the STOP or the SPND bit

is set. Cleared by H_RESET or

S_RESET and is unaffected by

STOP.

INTL

Internal Loopback. See the de-

scription of LOOP (CSR15, bit 2).

Read/Write accessible only when

either the STOP or the SPND bit

is set.

AM79C971VCW Datasheet(PDF) 131 Page - Advanced Micro Devices

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