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AM79C978VC/W Datasheet(PDF) 42 Page - Advanced Micro Devices |
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AM79C978VC/W Datasheet(HTML) 42 Page - Advanced Micro Devices |
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42 / 261 page ![]() 42 Am79C978 Figure 12. Slave Cycle Data Parity Error Response Master Bus Interface Unit The master Bus Interface Unit (BIU) controls the acqui- sition of the PCI bus and all accesses to the initializa- tion block, descriptor rings, and the receive and transmit buffer memory. Table 7 shows the usage of PCI commands by the Am79C978 controller in master mode. Bus Acquisition The microcode will determine when a DMA transfer should be initiated. The first step in any bus master transfer is to acquire ownership of the bus. This task is handled by synchronous logic within the BIU. Bus own- ership is requested with the REQ signal and ownership is granted by the arbiter through the GNT signal. Figure 13 shows the Am79C978 controller bus acquisi- tion. REQ is asserted and the arbiter returns GNT while ano ther bu s m a st er is tra n s f er ri ng d a ta. T h e Am79C978 controller waits until the bus is idle (FRAME and IRDY deasserted) before it starts driving AD[31:0] and C/BE[3:0] on clock 5. FRAME is asserted at clock 5 indicating a valid address and command on AD[31:0] and C/BE[3:0]. The Am79C978 controller does not use address stepping which is reflected by FRAME CLK AD IRDY TRDY C/BE DEVSEL PAR ADDR CMD PAR 1 2345678 10 9 DATA PAR BE PERR 22206B-15 Table 7. Master Commands C[3:0] Command Use 0000 Interrupt Acknowledge Not used 0001 Special Cycle Not used 0010 I/O Read Not used 0011 I/O Write Not used 0100 Reserved 0101 Reserved 0110 Memory Read Read of the initialization block and descriptor rings Read of the transmit buffer in non-burst mode 0111 Memory Write Write to the descriptor rings and to the receive buffer 1000 Reserved 1001 Reserved 1010 Configuration Read Not used 1011 Configuration Write Not used 1100 Memory Read Multiple Read of the transmit buffer in burst mode 1101 Dual Address Cycle Not used 1110 Memory Read Line Read of the transmit buffer in burst mode 1111 Memory Write Invalidate Not used Table 7. Master Commands (Continued) |
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