1

2

3

4

8

7

6

5

NC

NC

NC

NC =NoInternalConnection

NOTE:Thedevicewiththepower-downoptiondefaultstotheONstateifnosignalisappliedtothePDpin.Additionally,theREFpin

functionalrangeisfromV

to(V

4V).

S

S+

-

-

1

2

3

4

8

7

6

5

REF

NC

NC=NoInternalConnection

PD

THS3110

THS3111

D,DGN

TOPVIEW

D,DGN

TOPVIEW

THS3110

THS3111

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGED DEVICE

PLASTIC SMALL OUTLINE SOIC (D)

SYMBOL

THS3110CD

THS3110CDGN

0°C to +70°C

BJB

THS3110CDR

THS3110CDGNR

THS3110ID

THS3110IDGN

–40°C to +85°C

BIR

THS3110IDR

THS3110IDGNR

THS3111CD

THS3111CDGN

0°C to +70°C

BJA

THS3111CDR

THS3111CDGNR

THS3111ID

THS3111IDGN

–40°C to +85°C

BIS

THS3111IDR

THS3111IDGNR

(1)

For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2)

The PowerPAD is electrically isolated from all other pins.

DISSIPATION RATINGS TABLE

POWER RATING

PACKAGE

38.3

95

1.05 W

421 mW

4.7

58.4

1.71 W

685 mW

(1)

These data were taken using the JEDEC standard low-K test PCB. For the JEDEC proposed high-K test PCB, the

(2)

These data were taken using 2 oz. trace and copper pad that is soldered directly to a 3 inch × 3 inch (76,2 mm × 76,2 mm) PCB. For

further information, refer to the Application Information section of this data sheet.

2

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Product Folder Link(s): THS3110 THS3111