STM8S103F2 datasheet(26/117 Pages) STMICROELECTRONICS

26 / 117 page

Alternate function

after remap [option

bit]

Default

alternate

function

Main

function

(after

reset)

Output

Input

Type

Pin name

Pin no.

Speed

High sink

(1)

Ext.

interr.

wpu

floating

UFQFPN20

TSSOP/SO20

Analog input 6/

UART1 data

receive

Port D6

I/O

PD6/ AIN6/

UART1 _RX

Reset

I/O

NRST

Resonator/

crystal in

Port A1

I/O

PA1/ OSCIN

(2)

Resonator/

crystal out

Port A2

I/O

PA2/ OSCOUT

Digital ground

VSS

1.8 V regulator capacitor

VCAP

Digital power supply

VDD

SPI master/ slave

select [AFR1]

Timer 2

channel 3

Port A3

I/O

PA3/ TIM2_ CH3

[SPI_ NSS]

Timer 1 - break

input [AFR4]

C data

Port B5

(3)

I/O

PB5/ I

C_ SDA

[TIM1_ BKIN]

ADC external

trigger [AFR4]

C clock

Port B4

(3)

I/O

PB4/ I

C_ SCL

Top level interrupt

[AFR3] Timer 1 -

Timer 1 -

channel 3

Port C3

I/O

PC3/ TIM1_CH3

[TLI] [TIM1_

CH1N]

inverted channel 1

[AFR7]

Timer 1 - inverted

channel 2 [AFR7]

Configurable

clock

output/Timer 1

Port C4

I/O

PC4/ CLK_CCO/

TIM1_

CH4/AIN2/[TIM1_

CH2N]

- channel

4/Analog input

Timer 2 - channel 1

[AFR0]

SPI clock

Port C5

I/O

PC5/ SPI_SCK

[TIM2_ CH1]

Timer 1 - channel 1

[AFR0]

SPI master

out/slave in

Port C6

I/O

PC6/ SPI_MOSI

[TIM1_ CH1]

Timer 1 - channel 2

[AFR0]

SPI master in/

slave out

Port C7

I/O

PC7/ SPI_MISO

[TIM1_ CH2]

SWIM data

interface

Port D1

I/O

PD1/ SWIM

Timer 2 - channel 3

[AFR1]

Analog input 3

Port D2

I/O

PD2/AIN3/[TIM2_

CH3]

Analog input 4/

Timer 2 -

Port D3

I/O

PD3/ AIN4/ TIM2_

CH2/ ADC_ ETR

channel 2/ADC

external trigger

(1)

I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the total driven current must respect the absolute

maximum ratings.

(2)

When the MCU is in halt/active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for waking up the device. In this mode, the output

state of PA1 is not driven. It is recommended to use PA1 only in input mode if halt/active-halt is used in the application.

(3)

In the open-drain output column, "T" defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDD are not implemented).

DocID15441 Rev 9

26/117

STM8S103K3 STM8S103F3 STM8S103F2

Pinout and pin description

STM8S103F2 Datasheet(PDF) 26 Page - STMicroelectronics

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