TMS320C44PDB50 datasheet(21/52 Pages) TI

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TMS320C44

DIGITAL SIGNAL PROCESSOR

SPRS031C − AUGUST 1994 − REVISED MARCH 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

communication-port-software reset (continued)

When used in conjunction with the communication-port direction pins and NMI bus-grant, an effective method

of error detection and correction can be achieved. A subroutine showing how to reset communication port 1 is

given in Figure 3.

; −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−-−−−;

; RESET1:Flushes FIFOs data for communication port 1;

; −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−-−−−;

RESET1 push

AR0

; Save registers

push

;

push

;

ldhi

010h,AR0

; Set AR0 to base address of COM 1

050h,AR0

;

FLUSH: rpts

; Flush FIFO data with back-to-back write

sti

R0,*+AR0(3)

;

rpts

; Wait

nop

;

ldi

*+AR0(0),R0

; Check for new data from other port

and

01FE0h,R0

;

bnz

FLUSH

;

pop

; Restore registers

pop

;

pop

AR0

;

rets

; Return

Figure 3. Example of Communication-Port-Software Reset

NMI with bus-grant feature

The C44 devices have a software-configurable feature that allows forcing the internal-peripheral bus ready

when the NMI signal is asserted. The NMI bus-grant feature is enabled when bits 19 and 18 of the status register

(ST) are set to 10b. When enabled, a peripheral bus-grant signal is generated on the falling edge of NMI. If NMI

is asserted and this feature is not enabled, the CPU stalls on access to the peripheral bus if it is not ready. A

stall condition occurs when writing to a full output FIFO or reading an empty input FIFO. This feature is useful

in correcting communication-port errors when used in conjunction with the communication-port software-reset

feature.

IDLE2 clock-stop power-down mode

The C44 has a clock-stop mode, or power-down mode (IDLE2) to achieve extremely low power consumption.

When an IDLE2 instruction is executed, the clocks are halted with H1 held high. (Exiting IDLE2 requires

asserting one of the IIOF3−IIOF0 pins configured as an external interrupt.) A macro showing how to generate

the IDLE2 opcode is given in Figure 4. During this power-down mode:

D No instructions are executed.

D The CPU, peripherals, and internal memory retain their previous state.

D The external-bus outputs are idle. The address lines remain in their previous state; the data lines are in the

high-impedance state; and the output-control signals are inactive.

TMS320C44PDB50 Datasheet(PDF) 21 Page - Texas Instruments

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