COM20020ILJP datasheet(27/72 Pages) MICROCHIP

27 / 72 page

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Datasheet

SMSC COM20020I Rev D

Page 27

Revision 12-05-06

DATASHEET

Note 6.1

(R/W) This bit can be Written or Read. For more information see Appendix C -

Software

Identification of the COM20020 Rev B, Rev C and Rev D.

Table 6.2 - Write Register Summary

ADDR

MSB

WRITE

LSB

RI/TR1

EXCNAK

RECON

NEW

NEXTID

TA/

TTA

INTERRUPT

MASK

COMMAND

RD-

DATA

AUTO-

INC

A10

ADDRESS

PTR HIGH

ADDRESS

PTR LOW

DATA

(R/W)

Note 6.2

(R/W)

Note 6.2

SUB-

AD2

SUB-

AD1

SUB-

AD0

SUBADR

RESET

CCHEN

TXEN

ET1

ET2

BACK-

PLANE

SUB-

AD1

SUB-

AD0

CONFIG-

URATION

07-0

TID7

TID6

TID5

TID4

TID3

TID2

TID1

TID0

TENTID

07-1

NID7

NID6

NID5

NID4

NID3

NID2

NID1

NID0

NODEID

07-2

P1-

MODE

FOUR

NAKS

RCV-

ALL

CKP3

CKP2

CKP1

SLOW-

ARB

SETUP1

07-3

TEST

07-4

RBUS-

TMG

CKUP1

CKUP0

NO-

SYNC

RCN-

TM1

RCN-

TM0

SETUP2

Note 6.2

(R/W) This bit can be Written or Read. For more information see Appendix C -

Software

Identification of the COM20020 Rev B, Rev C and Rev D.

6.2

Internal Registers

The COM20020ID contains 14 internal registers. Table 6.1 and Table 6.2 illustrate the COM20020ID

6.2.1

Interrupt Mask Register (IMR)

The COM20020ID is capable of generating an interrupt signal when certain status bits become true. A

write to the IMR specifies which status bits will be enabled to generate an interrupt. The bit positions in the

IMR are in the same position as their corresponding status bits in the Status Register and Diagnostic

Status Register. A logic "1" in a particular position enables the corresponding interrupt. The Status bits

capable of generating an interrupt include the Receiver Inhibited bit, New Next ID bit, Excessive NAK bit,

Reconfiguration Timer bit, and Transmitter Available bit. No other Status or Diagnostic Status bits can

generate an interrupt.

The six maskable status bits are ANDed with their respective mask bits, and the results are ORed to

produce the interrupt signal. An RI or TA interrupt is masked when the corresponding mask bit is reset

to logic "0", but will reappear when the corresponding mask bit is set to logic "1" again, unless the interrupt

status condition has been cleared by this time. A RECON interrupt is cleared when the "Clear Flags"

command is issued. An EXCNAK interrupt is cleared when the "POR Clear Flags" command is issued. A

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