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AS1358 / AS1359

Datasheet - Application In form atio n

Total Thermal Path Resistance:

(EQ 6)

ºC

(EQ 7)

9.5 Explanation of Steady State Specifications

9.5.1 Line Regulation

Line regulation is defined as the change in output voltage when the input (or line) voltage is changed by a known quantity. It is a measure of the

regulator’s ability to maintain a constant output voltage when the input voltage changes. Line regulation is a measure of the DC open loop gain

of the error amplifier. More generally:

Line Regulation =

and is a pure number

(EQ 8)

available with numerous output voltage trim options.

Line Regulation =

% / V

(EQ 9)

9.5.2 Load Regulation

Load regulation is defined as the change of the output voltage when the load current is changed by a known quantity. It is a measure of the

regulator’s ability to maintain a constant output voltage when the load changes. Load regulation is a measure of the DC closed loop output

resistance of the regulator. More generally:

Load Regulation =

and is units of ohms (

)(EQ 10)

In practise, load regulation is referred to the regulator output voltage in terms of % / mA. This is particularly useful when the same regulator is

available with numerous output voltage trim options.

Load Regulation =

% / mA

(EQ 11)

9.5.3 Setting Accuracy

The regulator is supplied pre-trimmed, so that the output voltage accuracy is fully defined in the output voltage specification.

9.5.4 Total Accuracy

Away from dropout, total steady state accuracy is the sum of setting accuracy, load regulation and line regulation. Generally:

Total % Accuracy = Setting % Accuracy + Load Regulation % + Line Regulation %

(EQ 12)

9.6 Explanation of Dynamic Specifications

9.6.1 Power Supply Rejection Ratio (PSRR)

Known also as Ripple Rejection, this specification measures the ability of the regulator to reject noise and ripple beyond DC. PSRR is a

summation of the individual rejections of the error amplifier, reference and AC leakage through the series pass transistor. The specification, in

the form of a typical attenuation plot with respect to frequency, shows up the gain bandwidth compromises forced upon the designer in low

quiescent current conditions. Generally:

PSSR =

dB using lower case

to indicate AC values

(EQ 13)

Power supply rejection ratio is fixed by the internal design of the regulator. Additional rejection must be provided externally.

R



JA

R



JC

R



CS

R



SA

++

=



R



JA



 T

AMB

+

=

V

OUT

V

IN

----------------

V

OUT

V

IN

----------------

100

------------



V

OUT

I

OUT

----------------

V

OUT

I

OUT

----------------

100

V

OUT

----------------



20Log

V

OUT

V

IN

----------------

