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AS1363

Datasheet - Application In form atio n

9.6 Explanation of Dynamic Specifications

9.6.1 Power Supply Rejection Ratio (PSRR)

Known also as Ripple Rejection, this specification measures the ability of the regulator to reject noise and ripple beyond DC. PSRR is a

summation of the individual rejections of the error amplifier, reference and AC leakage through the series pass transistor. The specification, in

the form of a typical attenuation plot with respect to frequency, shows up the gain bandwidth compromises forced upon the designer in low

quiescent current conditions. Generally:

PSSR =

dB using lower case

to indicate AC values

(EQ 14)

Power supply rejection ratio is fixed by the internal design of the regulator. Additional rejection must be provided externally.

9.6.2 Output Capacitor ESR

The series regulator is a negative feedback amplifier, and as such is conditionally stable. The ESR of the output capacitor is usually used to

cancel one of the open loop poles of the error amplifier in order to produce a single pole response. Excessive ESR values may actually cause

instability by excessive changes to the closed loop unity gain frequency crossover point. The range of ESR values for stability is usually shown

either by a plot of stable ESR versus load current, or a limit statement in the datasheet.

Some ceramic capacitors exhibit large capacitance and ESR variations with temperature. Z5U and Y5V capacitors may be required to ensure

Larger output capacitor values (10µF max) help to reduce noise and improve load transient-response, stability and power-supply rejection.

9.6.3 Input Capacitor

at the input.

9.6.4 Noise

The regulator output is a DC voltage with noise superimposed on the output. The noise comes from three sources; the reference, the error

amplifier input stage, and the output voltage setting resistors. Noise is a random fluctuation and if not minimized in some applications, will

produce system problems.

9.6.5 Transient Response

The series regulator is a negative feedback system, and therefore any change at the output will take a finite time to be corrected by the error

loop. This “propagation time” is related to the bandwidth of the error loop. The initial response to an output transient comes from the output

capacitance, and during this time, ESR is the dominant mechanism causing voltage transients at the output. More generally:

Units are Volts, Amps, Ohms.

(EQ 15)

Thus an initial +50mA change of output current will produce a -12mV transient when the ESR=240m

. Remember to keep the ESR within

stability recommendations when reducing ESR by adding multiple parallel output capacitors.

After the initial ESR transient, there follows a voltage droop during the time that the LDO feedback loop takes to respond to the output change.

This drift is approx. linear in time and sums with the ESR contribution to make a total transient variation at the output of:

Units are Volts, Seconds, Farads, Ohms.

(EQ 16)

Where:

T = Propagation delay of the LDO

This shows why it is convenient to increase the output capacitor value for a better support for fast load changes. Of course the formula holds for

t < “propagation time”, so that a faster LDO needs a smaller cap at the load to achieve a similar transient response. For instance 50mA load

current step produces 50mV output drop if the LDO response is 1usec and the load cap is 1µF.

There is also a steady state error caused by the finite output impedance of the regulator. This is derived from the load regulation specification

discussed above.

20Log

V

OUT

V

IN

----------------



V

TRANSIENT

I

OUTPUT

R

ESR



=

V

TRANSIENT

I

OUTPUT

=

R

ESR

T

C

LOAD

----------------

+





