AS3909 datasheet(27/77 Pages) AMSCO

27 / 77 page

ams Datasheet, Confidential: 2013-Oct [3-02]

AS3909/AS3910 – 27

Appl icatio n I n f o rm a t i o n

Reading Received Data from FIFO

Reading received data from the FIFO is similar to reading data

from an addressable registers. Difference is that in case of

reading more bytes they all come from the FIFO. The command

mode code 10 indicates FIFO operations. In case of reading the

received data from the FIFO all bits

<C5 – C0> are set to 1. On the following SCLK rising edges the

data from FIFO appears as in case of read data from addressable

registers. In case the command is terminated by putting SEN

low before a packet of 8 bits composing one byte is read that

particular byte is considered unread and will be the first one

read in next FIFO read operation.

Interrupt Interface

When an interrupt condition is met the source of interrupt bit

is set in the Interrupt Register and the INTR pin transitions to

high.

The microcontroller then reads the Interrupt Register to

distinguish between different interrupt sources. After the

Interrupt Register is read its content is reset to 0 and INTR pin

signal transitions to low.

Note(s):There may be more than one Interrupt Register bit set

in case the microcontroller did not immediately read the

Interrupt Register after the INTR signal was set and another event

causing interrupt occurred.

In case an interrupt from a certain source is not required it can

be disabled by setting corresponding bit in the Mask Interrupt

interrupt is not produced, but the source of interrupt bit is still

set in Interrupt Register.

After reading the Interrupt Register the 13.56MHz clock coming

from the oscillator is used to produce a reset signal which clears

it and resets INTR signal. Practically in all interrupt cases the

oscillator is running when an interrupt is produced. The only

exception is the interrupt in the Initial NFC Target mode where

only the Target Activation Detector is operating. In this case the

interrupt is cleared with first SCLK rising edge following reading

of the Interrupt Register (an extra dummy CLK pulse during

reading of the Interrupt Register or first SCLK pulse of the next

SPI command will do the job).

Figure 19:

Serial Peripheral Interface (4-wire Interface) Signal Lines

Name

Signal

Signal Level

Description

INTR

Digital Output

CMOS

Interrupt Output pin

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