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AS5055

Datasheet - Application In form atio n

8 Application Information

The benefits of the AS5055 device are as follows:



Complete system-on-chip



Low power consumption



Low operating voltage



Easy to use SPI interface

8.1 SPI Interface

The 16-bit SPI Interface enables read / write access to the register blocks and is compatible to a standard micro controller interface. The SPI

module is active as soon as /SS pin is pulled low. The AS5055 then reads the digital value on the MOSI (master out slave in) input with every

falling edge of SCK and writes on its MISO (master in slave out) output with the rising edge. After 16 clock cycles /SS has to be set back to a high

status in order to reset some parts of the interface core. The SPI Interface can be set in two different modes: 3-wire mode or 4-wire mode.

Notes:

1. The wire mode selection is read during the POWER-UP state and can be changed with a power on reset or a software reset command.

2. For more stability on the SPI Interface, it is very important to place filters. The filter must be placed close to the driving outputs. For

further information, please refer to the application note AN5000_SPI_Interface.

8.1.1 SPI Interface Signals (4-Wire Mode, Wire_mode = 1)

The AS5055 only supports slave operation mode. Therefore SCK for the communication as well as the /SS signal has to be provided by the test

equipment. The following picture shows a basic interconnection diagram with one master and an AS5055 device and a principle schematic of the

interface core.

Figure 10. SPI Interface Connection

Because the interface has to decode the sent command before it can react and provide data the response of the chip to a specific command

applied at a time T can be accessed in the next transmission cycle ending at T + TCOM.

Table 15. Wire Mode Selection

Wire Mode Selection (pad 14)

wire_mode = LO

3-wire mode

wire_mode = HI

4-wire mode

SPI_CLK

MOSI

MISO

SCK

SS/

RXSR

Interface Core

MISO

MOSI

Master Device

(Tester)

AS5055

TXSR

RXSPI

TXSPI