AT17C/LV512/010

2

Controlling The High-Density AT17 Series Serial EEPROMs

Most connections between the FPGA device and the Serial

EEPROM are simple and self-explanatory:

• The DATA output of the high-density AT17 Series drives

DIN of the FPGA devices.

• The master FPGA CCLK output drives the CLK input of

the high-density AT17 Series.

• The CEO output of any AT17C/LV512/010 drives the CE

input of the next AT17C/LV512/010 in a cascade chain of

PROMs.

ISP).

READY is available as an open-collector indicator of the

device’s RESET status; it is driven Low while the device is

in its POWER-ON RESET cycle and released (tri-stated)

when the cycle is complete.

There are two different ways to use the inputs CE and OE,

as shown in the AC Characteristics waveforms.

Condition 1

The simplest connection is to have the FPGA D/P output

drive both CE and RESET/OE in parallel (Figure 1). Due to

its simplicity, however, this method will fail if the FPGA

receives an external reset condition during the configura-

tion cycle. If a system reset is applied to the FPGA, it will

abort the original configuration and then reset itself for a

new configuration, as intended. Of course, the high-density

AT17 Series does not see the external reset signal and will

not reset its internal address counters and, consequently,

will remain out of sync with the FPGA for the remainder of

the configuration cycle.

Condition 2

The FPGA D/P output drives only the CE input of the high-

density AT17 Series, while its OE input is driven by the

inversion of the input to the FPGA RESET input pin. This

connection works under all normal circumstances, even

when the user aborts a configuration before D/P has gone

High. A High lev e l on the RES ET/OE inpu t to the

AT17C/LVxxx – during FPGA reset – clears the Configura-

tor’s internal address pointer, so that the reconfiguration

starts at the beginning. The high-density AT17 Series does

not require an inverter since the RESET polarity is pro-

grammable.

Block Diagram