TSL210 datasheet(4/13 Pages) AMSCO

4 / 13 page

TSL210

640 × 1 LINEAR SENSOR ARRAY

TAOS039D − AUGUST 2011

The LUMENOLOGY

r Company

E 2011, TAOS Inc.

www.taosinc.com

The output and reset of the integrators in each section are controlled by a 128-bit shift register and reset logic.

An output cycle is initiated by clocking in a logic 1 on SI. As the SI pulse is clocked through the shift register,

the charge stored on the sampling capacitors of each pixel is sequentially connected to a charge-coupled output

amplifier that generates a voltage on analog output AO (given above). After being read, the pixel integrator is

then reset, and the next integration period begins for that pixel. On the 129th clock rising edge, the SO pulse

is clocked out on SO signifying the end of the read cycle. The section is then ready for another read cycle. The

SO of each section can be connected to SI on the next section in the array (Figure 4). SO can be used to signify

the read is complete.

AO is driven by a source follower that requires an external pulldown resistor (330-

Ω typical). The output is

nominally 0 V for no light input, 2 V for normal white-level, and 3.4 V for saturation light level. When the device

is not in the output phase, AO is in a high impedance state.

A 0.1

μF bypass capacitor should be connected between VDD and ground as close as possible to the device.

TSL210 Datasheet(PDF) 4 Page - ams AG