AT28C040

3

Device Operation

READ: The AT28C040 is accessed like a static RAM.

When CE and OE are low and WE is high, the data stored

at the memory location determined by the address pins is

asserted on the outputs. The outputs are put in the high

impedance state when either CE or OE is high. This dual-

line control gives designers flexibility in preventing bus con-

tention in their systems.

BYTE WRITE: A low pulse on the WE or CE input with CE

or WE low (respectively) and OE high initiates a write cycle.

The address is latched on the falling edge of CE or WE,

whichever occurs last. The data is latched by the first rising

edge of CE or WE. Once a byte write has been started, it

will automatically time itself to completion. Once a pro-

gramming operation has been initiated and for the duration

of t

tion.

PAGE WRITE: The page write operation of the AT28C040

allows 1 to 256 bytes of data to be written into the device

during a single internal programming period. A page write

operation is initiated in the same manner as a byte write;

the first byte written can then be followed by 1 to 255 addi-

tional bytes. Each successive byte must be written within

150

µs (t

exceeded, the AT28C040 will cease accepting data and

commence the internal programming operation. All bytes

during a page write operation must reside on the same

page as defined by the state of the A8 - A18 inputs. For

each WE high to low transition during the page write opera-

tion, A8 - A18 must be the same.

The A0 to A7 inputs specify which bytes within the page are

to be written. The bytes may be loaded in any order and

may be altered within the same load period. Only bytes

which are specified for writing will be written; unnecessary

cycling of other bytes within the page does not occur.

DATA POLLING: The AT28C040 features DATA Polling to

indicate the end of a write cycle. During a byte or page

write cycle an attempted read of the last byte written will

result in the complement of the written data to be presented

on I/O7. Once the write cycle has been completed, true

data is valid on all outputs, and the next write cycle may

begin. DATA Polling may begin at anytime during the write

cycle.

TOGGLE BIT: In addition to DATA Polling, the AT28C040

provides another method for determining the end of a write

cycle. During the write operation, successive attempts to

read data from the device will result in I/O6 toggling

between one and zero. Once the write has completed, I/O6

will stop toggling and valid data will be read. Reading the

toggle bit may begin at any time during the write cycle.

DATA PROTECTION: If precautions are not taken, inad-

vertent writes may occur during transitions of the host sys-

tem power supply. Atmel has incorporated both hardware

and software features that will protect the memory against

inadvertent writes.

HARDWARE PROTECTION: Hardware features protect

against inadvertent writes to the AT28C040 in the following

function is inhibited; (b) V

reached 3.8V the device will automatically time out 5 ms

(typical) before allowing a write: (c) write inhibit - holding

any one of OE low, CE high or WE high inhibits write

cycles; (d) noise filter - pulses of less than 15 ns (typical)

on the WE or CE inputs will not initiate a write cycle.

SOFTWARE DATA PROTECTION: A software controlled

data protection feature has been implemented on the

AT28C040. When enabled, the software data protection

(SDP), will prevent inadvertent writes. The SDP feature

may be enabled or disabled by the user; the AT28C040 is

shipped from Atmel with SDP disabled.

SDP is enabled when the host system issues a series of

three write commands; three specific bytes of data are writ-

ten to three specific addresses (refer to Software Data Pro-

tection Algorithm). After writing the 3-byte command

tected against inadvertent write operations. It should be

noted that once protected, the host can still perform a byte

or page write to the AT28C040. To do so, the same 3-byte

command sequence used to enable SDP must precede the

data to be written.

Once set, SDP will remain active unless the disable com-

mand sequence is issued. Power transitions do not disable

SDP, and SDP will protect the AT28C040 during power-up

and power-down conditions. All command sequences must

conform to the page write timing specifications. The data in

the enable and disable command sequences is not written

to the device, and the memory addresses used in the

sequence may be written with data in either a byte or page

write operation.

After setting SDP, any attempt to write to the device without

the 3-byte command sequence will start the internal write

timers. No data will be written to the device; however, for

ing operations.

DEVICE IDENTIFICATION: An extra 256 bytes of

E

tification. By raising A9 to 12V

± 0.5V and using address

locations 7FF80H to 7FFFFH, the bytes may be written to

or read from in the same manner as the regular memory

array.

OPTIONAL CHIP ERASE MODE: The entire device can

be erased using a 6-byte software erase code. Please see

Software Chip Erase application note for details.