Figure 5. SC and EZ1/EZ2 Validation for AT88SC101/102

A) Compare sequence of the security code or the application zone erase key.

B) First bit which is at a logic 1, in the false attempts counter to validate SC, or in the recharge counter to validate EZ.

C) Program sequence attempts to write a 0 over the 1 currently at this address.

D) The chip outputs the new state of the bit. If a 0 has been successfully programmed, SC or EZ is set on the rising edge

of PGM. (Note: If CLK rises when PGM is low, the validation is aborted.)

E) This program sequence will erase either the false attempts counter or the application zone.

F) Chip outputs state of the current bit. If the erase was successful, the chip will output a 1 if the current bit is in the false

attempts counter. The chip will output a 0 if the current bit is in the recharge counter.

G) On the falling edge of clock, the address is incremented and the state of the next bit is output.

Note:

1. The address does not change from operations B to F.

AT88SC101/102

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