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ATMEGA161-4AI Datasheet(PDF) 64 Page - ATMEL Corporation |
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ATMEGA161-4AI Datasheet(HTML) 64 Page - ATMEL Corporation |
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64 / 134 page  ATmega161(L) 64 4. For each received data byte, the receiving MCU will set the receive complete flag (RXCn in UCSRnA. In 8-bit mode, the receiving MCU will also generate a framing error (FEn in UCSRnA set), since the stop bit is zero. The other slave MCUs, which still have the MPCMn bit set, will ignore the data byte. In this case, the UDRn register and the RXCn, FEn, or flags will not be affected. 5. After the last byte has been transferred, the process repeats from step 2. UART Control UART0 I/O Data Register – UDR0 UART1 I/O Data Register – UDR1 The UDRn register is actually two physically separate registers sharing the same I/O address. When writing to the register, the UART Transmit Data register is written. When reading from UDRn, the UART Receive Data register is read. UART0 Control and Status Registers – UCSR0A UART1 Control and Status Registers – UCSR1A • Bit 7 - RXC0/RXC1: UART Receive Complete This bit is set (one) when a received character is transferred from the Receiver Shift register to UDRn. The bit is set regard- less of any detected framing errors. When the RXCIEn bit in UCSRnB is set, the UART Receive Complete interrupt will be executed when RXCn is set(one). RXCn is cleared by reading UDRn. When interrupt-driven data reception is used, the UART Receive Complete Interrupt routine must read UDRn in order to clear RXCn, otherwise a new interrupt will occur once the interrupt routine terminates. • Bit 6 - TXC0/TXC1: UART Transmit Complete This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out and no new data has been written to UDRn. This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIEn bit in UCSRnB is set, setting of TXCn causes the UART Transmit Complete interrupt to be executed. TXCn is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXCn bit is cleared (zero) by writing a logical one to the bit. Bit 7 6 543 210 $0C ($2C) MSB LSB UDR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 Bit 7 6 543 210 $03 ($23) MSB LSB UDR1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 Bit 7 6 543 210 $0B ($2B) RXC0 TXC0 UDRE0 FE0 OR0 - U2X0 MPCM0 UCSR0A Read/Write R R/W R R R R R/W R/W Initial value 0 0 1 0 0 0 0 0 Bit 7 6 543 210 $02 ($22) RXC1 TXC1 UDRE1 FE1 OR1 - U2X1 MPCM1 UCSR1A Read/Write R R/W R R R R R/W R/W Initial value 0 0 1 0 0 0 0 0 |
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