2

4768B–INDCO–10/05

T2117

Figure 1-1.

Block Diagram with Typical Circuit, Period Group Control 0 to 100%

2.

Pin Configuration

Figure 2-1.

Pinning DIP8/SO8

Ramp

generator

Pulse

amplifier

Comparator

18 k

Ω/

2 W

L

Synchronization

Supply

Full-wave logic

+

-

Reference voltage

1.4 V

1

3

4

R

4

100 k

Ω

2

8

5

C

2

2.2 µF/

10 V

12 k

Ω

min

max

100 k

Ω

18 k

Ω

7

6

220 k

Ω

100

Ω

Load

1000 W

V

N

R

2

(250 V~)

MT2

MT1

GND

+

100 µF/

16 V

T2117

-V

S

(R

R

1

D

1

C

1

R

3

R

6

R

5

1

2

3

4

8

7

6

5

RAMP

CRAMP

POSIN

NEGIN

VSYNC

GND

OUTPUT

VS

T2117

Table 2-1.

Pin Description

Pin

Symbol

Function

1

RAMP

Ramp output

2

CRAMP

Ramp capacitor

3

POSIN

Non-inverting comparator input

4

NEGIN

Inverting comparator input

5

VS

Supply voltage

6

OUTPUT

Trigger pulse output

7

GND

Ground

8

VSYNC

Voltage synchronization