5-208

FAST AND LS TTL DATA

SN54/74LS125A

• SN54/74LS126A

Symbol

Parameter

Limits

Unit

Test Conditions

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

VIH

Input HIGH Voltage

2.0

V

Guaranteed Input HIGH Voltage for

All Inputs

VIL

Input LOW Voltage

54

0.7

V

Guaranteed Input LOW Voltage for

All Inputs

VIL

Input LOW Voltage

74

0.8

V

Guaranteed Input LOW Voltage for

All Inputs

VIK

Input Clamp Diode Voltage

– 0.65

– 1.5

V

VCC = MIN, IIN = – 18 mA

VOH

Output HIGH Voltage

54

2.4

V

VCC = MIN, IOH = MAX, VIN = VIH

or VIL per Truth Table

VOH

Output HIGH Voltage

74

2.4

V

VCC = MIN, IOH = MAX, VIN = VIH

or VIL per Truth Table

VOL

Output LOW Voltage

54, 74

0.25

0.4

V

IOL = 12 mA

VCC = VCC MIN,

VIN = VIL or VIH

per Truth Table

VOL

Output LOW Voltage

74

0.35

0.5

V

IOL = 24 mA

VIN = VIL or VIH

per Truth Table

IOZH

Output Off Current HIGH

20

µA

VCC = MAX, VOUT = 2.4 V

IOZL

Output Off Current LOW

– 20

µA

VCC = MAX, VOUT = 0.4 V

IIH

Input HIGH Current

20

µA

VCC = MAX, VIN = 2.7 V

IIH

Input HIGH Current

0.1

mA

VCC = MAX, VIN = 7.0 V

IIL

Input LOW Current

– 0.4

mA

VCC = MAX, VIN = 0.4 V

IOS

Short Circuit Current (Note 1)

– 40

–225

mA

VCC = MAX

ICC

Power Supply Current

LS125A

20

mA

VCC = MAX

VIN = 0 V, VE = 4.5 V

ICC

Power Supply Current

LS126A

22

mA

VCC = MAX

VIN = 0 V, VE = 0 V

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

Symbol

Parameter

Limits

Unit

Test Conditions

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

tPLH

Propagation Delay,

Data to Output

LS125A

9.0

15

ns

Figure 2

VCC = 5.0 V

CL = 45 pF

RL = 667 Ω

tPLH

Propagation Delay,

Data to Output

LS126A

9.0

15

ns

Figure 2

VCC = 5.0 V

CL = 45 pF

RL = 667 Ω

tPHL

Propagation Delay,

Data to Output

LS125A

7.0

18

ns

Figure 2

VCC = 5.0 V

CL = 45 pF

RL = 667 Ω

tPHL

LS126A

8.0

18

VCC = 5.0 V

CL = 45 pF

RL = 667 Ω

tPZH

Output Enable Time

to HIGH Level

LS125A

12

20

ns

Figures 4, 5

CL = 45 pF

RL = 667 Ω

tPZH

Output Enable Time

to HIGH Level

LS126A

16

25

ns

Figures 4, 5

L = 667 Ω

tPZL

Output Enable Time

to LOW Level

LS125A

15

25

ns

Figures 3, 5

tPZL

Output Enable Time

to LOW Level

LS126A

21

35

ns

Figures 3, 5

tPHZ

Output Disable Time

from HIGH Level

LS125A

20

ns

Figures 4, 5

VCC = 5.0 V

CL = 5.0 pF

RL = 667 Ω

tPHZ

Output Disable Time

from HIGH Level

LS126A

25

ns

Figures 4, 5

VCC = 5.0 V

CL = 5.0 pF

RL = 667 Ω

tPLZ

Output Disable Time

from LOW Level

LS125A

20

ns

FIgures 3, 5

CL = 5.0 pF

RL = 667 Ω

tPLZ

Output Disable Time

from LOW Level

LS126A

25

ns

FIgures 3, 5

L = 667 Ω