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AFE2124 Datasheet(PDF) 4 Page - Burr-Brown (TI) |
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AFE2124 Datasheet(HTML) 4 Page - Burr-Brown (TI) |
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4 / 11 page  4 ® AFE2124 PIN CONFIGURATION Top View SSOP PIN DESCRIPTIONS PIN # TYPE NAME DESCRIPTION CHANNEL A 1 Output Data OutA Output Data Word 2 Input rx48xCLKA Receive Clock at 48x Baud Clock (23.032MHz for E1) 3 Input rxbaudCLKA Receive Baud Clock (584kHz for E1) 4 Input Data InA Input Data Word 5 Input tx48xCLKA Transmit Clock (584kHz for E1) 6 Input txbaudCLKA Transmit Baud Clock at 48x Baud Clock (584kHz for E1) 7 Power DVDD Digital Supply (+3.3V to +5V) 8 Ground DGND Digital Ground 9 Ground AGND Analog Ground 10 Output txLINE+A Transmit Line Driver Output, Positive 11 Power AVDD Analog Supply (+5V) 12 Output txLINE–A Transmit Line Driver Output, Negative 13 Ground AGND Analog Ground 14 Power AVDD Analog Supply (+5V) 15 Output REFNA Negative Reference Output 16 Output VCMA Common-Mode Voltage (buffered) 17 Output REFPA Positive Reference Output 18 Ground AGND Analog Ground 19 Ground AGND Analog Ground 20 Input rxLINE+A Positive Line Input 21 Input rxLINE–A Negative Line Input 22 Input rxHYB+A Positive Input from Hybrid Network 23 Input rxHYB–A Negative Input from Hybrid Network 24 Power AVDD Analog Supply (+5V) 25 Power AVDD Analog Supply (+5V) CHANNEL B 26 Input rxHYB–B Negative Input from Hybrid Network 27 Input rxHYB+B Positive Input from Hybrid Network 28 Input rxLINE–B Negative Line Input 29 Input rxLINE+B Postiive Line Input 30 Ground AGND Analog Ground 31 Ground AGND Analog Ground 32 Output REFPB Positive Reference Output 33 Output VCMB Common-Mode Voltage (buffered) 34 Output REFNB Negative Reference Output 35 Power AVDD Analog Supply (+5V) 36 Ground AGND Analog Ground 37 Output txLINE–B Transmit LIne Driver Output, Negative 38 Power AVDD Analog Supply (+5V) 39 Output txLINE+B Transmit Line Driver Output, Positive 40 Ground AGND Analog Ground 41 Ground DGND Digital Ground 42 Power DVDD Digital Supply (+3.3V to +5V) 43 Input txbaudCLKB Transmit Baud Clock (584kHz for E1) 44 Input tx48xCLKB Transmit Clock at 48x Baud Clock (28.032MHz for E1) 45 Input Data InB Input Data Word 46 Input rxbaudCLKB Receive Baud Clock (584kHz for E1) 47 Input rx48xCLKB Receive Clock at 48x Baud Clock (28.032MHz for E1) 48 Output Data OutB Output Data Word Data OutA rx48xCLKA rxbaudCLKA Data InA tx48xCLKA txbaudCLKA DV DD DGND AGND txLINE+A AV DD txLINE–A AGND AV DD REF NA V CMA REF PA AGND AGND rxLINE+A rxLINE–A rxHYB+A rxHYB–A AV DD Data OutB rx48xCLKB rxbaudCLKB Data InB tx48xCLKB txbaudCLKB DV DD DGND AGND txLINE+B AV DD txLINE–B AGND AV DD REF NB V CMB REF PB AGND AGND rxLINE+B rxLINE–B rxHYB+B rxHYB–B AV DD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 AFE2124 Channel A Channel B |
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