Crest factor reduction – Based on field-prov-

en technology, the GC5322’s CFR processing

block reduces the peak-to-average ratio (PAR)

for multi-channel/multi-carrier signals by

adding spectrally-shaped cancellation noise.

The CFR block has multiple stages, each having

configurable peak thresholds. This allows for

significant PAR reduction. Breakthrough power

efficiencies are achieved in the PA, while

maintaining spectral requirements and EVM

performance.

Digital pre-distortion – To limit possible

distortion in the transmit signal, the GC5322

includes an integrated DPD processing block.

The DPD block linearizes the PA, greatly

improving the adjacent channel leakage ratio

(ACLR). This allows PAs to meet stringent

spectral regulations and interference

requirements. Depending upon the PA, the

DPD block achieves ACLR improvements

of 20 to 30 dB or more.

The GC5322 interfaces directly to TI’s

TMS320C6727 DSP, which executes the

real-time adaptation algorithm. A real-time

feedback loop monitors the integrity of the

output signal to control the DPD’s operation.

The flexible algorithm supports multiple

PA architectures and emerging standards,

such as CDMA2000, WCDMA, TD-SCDMA,

OFDMA (WiMAX, LTE), HSPA and HSPA+.

Input

format

Gain

DUC

CFR

Fractional

resampler

DPD

ADC

interface

FB

TX

(LVDS)

MFIO

(ADC input/

test output)

BBCLK

DPDCLK

(LVDS)

Tramsmit

equalizer

MPU interface

SYNC

3

SYNC

OUT

UPDATA UPADDR

JTAG

RESETB SYNCD

(LVDS)

INT

BB

BBFR

4

OEB RDB WRB CEB

TDO

TCK

TRSTB

TDI

TMS

10

16

Feedback

equalizer

Real to complex

(or bypass)

Bulk

interpolation

+ mixer

Feedback NL

correction

DAC

interface

A detailed block diagram of the GC5322 showing the integration of three critical transmit functions:

DUC, CFR and DPD

GC5322

DUC-CFR-DPD

GC5322

DUC-CFR-DPD

C6727

DSP

Mixer

I/Q

I

Q

I

Q

I/Q

20 MHz RF card

20 MHz RF card

Mixer

HPA

HPA

DAC

DAC5682z

DAC5682z

ADS5527

ADS5527

ADC

DAC

ADC

I/Q

Modulator

TRF3703

I/Q

Modulator

TRF3703

SDRAM

(256 Mbit)

EMIF

SPI

EMIF

HPI

BB I/Q

Data

BB I/Q

Data

CPRI/

OBSAI

Host

processor

GC5322 in a dual-antenna configuration with up to 20 MHz of signal bandwidth