7

CAT25C32/64

Doc No. 25087 -00 8/99 SPI-1

Advanced Information

Figure 4. Read Instruction Timing

Byte Write

Once the device is in a Write Enable state, the user may

proceed with a write sequence by setting the

CS low,

issuing a write instruction via the SI line, followed by the

16-bit address (the three Most Significant Bits are don’t

care for 25C64 and four most significant bits are don't

care for 25C32), and then the data to be written. Pro-

gramming will start after the

CS is brought high. Figure

6 illustrates byte write sequence.

WRITE Sequence

The CAT25C32/64 powers up in a Write Disable state.

Prior to any write instructions, the WREN instruction

must be sent to CAT25C32/64. The device goes into

Write enable state by pulling the

CS low and then

clocking the WREN instruction into CAT25C32/64. The

CS must be brought high after the WREN instruction to

enable writes to the device. If the write operation is

initiated immediately after the WREN instruction without

CS being brought high, the data will not be written to the

array because the write enable latch will not have been

properly set. Also, for a successful write operation the

address of the memory location(s) to be programmed

must be outside the protected address field location

selected by the block protection level.

Figure 5. RDSR Instruction Timing

Note: Dashed Line= mode (1, 1) — — — —

Note: Dashed Line= mode (1, 1) — — — —

SK

SI

SO

0000001

1

BYTE ADDRESS*

0123456789

10

20

21

22

23

24

25

26

27

28

29

30

7

6

5

4

3

2

1

0

*Please check the instruction set table for address

CS

OPCODE

DATA OUT

MSB

HIGH IMPEDANCE

0

1

2

345

67

8

10

911

12

13

14

SCK

SI

DATA OUT

MSB

HIGH IMPEDANCE

OPCODE

SO

7

6

5

4

3

2

1

0

CS

00

0

00

1

0

1