| Electronic Components Datasheet Search |
|
CAT33C804APATE13 Datasheet(PDF) 13 Page - Catalyst Semiconductor |
|
|
|||||||||||||||||||||||||||||
CAT33C804APATE13 Datasheet(HTML) 13 Page - Catalyst Semiconductor |
|
13 / 14 page ![]() Preliminary CAT33C804A 13 Doc. No. 25044-00 2/98 1000 0011 Override the memory protection for the next instruction. READ Read Memory 1100 [A7–A0] (x16 organization) 1100 1001 1001 [A15–A8] [A7–A0] (x8 organization) Output the contents of the addressed memory location to the serial port. WRITE Write Memory 1100 [A7–A0] [D15–D8] [D7–D0] (x16 organization) 1100 0001 0001 [A15–A8] [A7–A0] [D7–D0] (x8 organization) Write the 8-bit or 16-bit data to the addressed memory location. After the instruction, address, and data have been entered, the self-timed program/erase cycle will start. The addressed memory location will be erased before data is written. The DO pin may be used to output the RDY/ BUSY status by having previously entered the ENBSY instruction. During the program/erase cycle, DO will output a LOW for BUSY during this cycle and a HIGH for READY after the cycle has been completed. ERASE Clear Memory 1100 [A7–A0] (x16 organization) 1100 0000 0000 [A15–A8] [A7–A0] (x8 organization) Erase data in the specified memory location (set memory to “1”). After the instruction and the address have been entered, the self-timed clear cycle will start. The DO pin may be used to output the RDY/ BUSY status by having previously entered the ENSBY instruction. During the clear cycle, DO will output a LOW for BUSY during this cycle and a HIGH for ready after the cycle has been completed. ERAL Clear All 1000 1000 1001 1001 Erase the data of all memory locations (all cells set to “1”). For protection against inadvertent chip clear, the ERAL instruction is required to be entered twice. Figure 16. WRAL Timing (x8 Format) 33C804 F17 33C804 F18 Note: (1) DO becomes low to indicate busy status if ENBSY was previously executed. If ENBSY was not previously executed, DO will be in the High-Z condition. CS DI HIGH-Z DO OP0–OP7 tEW BUSY(1) OP CODE OP0–OP7 OP CODE NEXT INSTRUCTION D0–D7 DATA Figure 17. WRAL Timing (x16 Format) CS DI HIGH-Z DO OP0–OP7 tEW BUSY(1) OP CODE OP0–OP7 OP CODE NEXT INSTRUCTION D8–D15 DATA D0–D7 DATA |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |