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ACPL-C87AT Datasheet(PDF) 13 Page - AVAGO TECHNOLOGIES LIMITED |
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ACPL-C87AT Datasheet(HTML) 13 Page - AVAGO TECHNOLOGIES LIMITED |
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13 / 14 page ![]() 13 Designing the input resistor divider 1. Choose the sensing current (Isense) for bus voltage. E.g., 1 mA 2. Determine R2, R2 = = Voltage input range ISENSE = 2 kΩ 2 V 1 mA R1 = (V+ – V-) • R2 Voltage input range – R2 R1 = (600 V – 0 V) • 2 kΩ 2 V – 2 kΩ = 598 kΩ (V+ – V-) • R2 R1 + R2 = Voltage input range, or 3. Determine R1 using voltage divider formula: R2 = = Voltage input range ISENSE = 2 kΩ 2 V 1 mA R1 = (V+ – V-) • R2 Voltage input range – R2 R1 = (600 V – 0 V) • 2 kΩ 2 V – 2 kΩ = 598 kΩ (V+ – V-) • R2 R1 + R2 = Voltage input range, or where (V+ – V-) is the high voltage input , E.g.: 0 to 600 V, R2 = = Voltage input range ISENSE = 2 kΩ 2 V 1 mA R1 = (V+ – V-) • R2 Voltage input range – R2 R1 = (600 V – 0 V) • 2 kΩ 2 V – 2 kΩ = 598 kΩ (V+ – V-) • R2 R1 + R2 = Voltage input range, or To reduce the voltage stress of a sole resistor, R1 can be a series of several resistors. Post Amplifier Circuit The output of ACPL-C87AT/BT is a differential output (VOUT+ and VOUT- pins). A post amplifier circuit is needed to convert the differential output to single ended output with a reference ground. The post amplifier circuit can also be configured to establish a desired gain if needed. It also functions as filter to high frequency chopper noise. The bandwidth can be adjusted by changing the feedback resistor and capacitor (R7 and C7). Adjusting this bandwidth to a minimum level helps minimize the output noise. Post op-amp resistive loading (R4, R5) should be equal or greater than 20 k W (Figure 31). Resistor values lower than this can affect the overall system error due to output impedance of isolation amplifier. The application circuit in Figure 28 features two op-amps to improve the linearity at voltage near 0 V caused by the limited headroom of the amplifier. The second op-amp can set the reference voltage to above 0 V. Shutdown Function ACPL-C87AT/BT has a shutdown function to disable the device and make the output (VOUT+ - VOUT-) low. A voltage of 5V on SHDN pin will shutdown the device producing an output (VOUT+ - VOUT-) of -2.6 V. To be able to control the SHDN function (example, from microprocessor), an opto- coupler (ACPL-M49T) is used. Total System Error Total system error is the sum of the resistor divider error, isolation amplifier error and post amplifier error. The resistor divider error is due to the accuracy of the resistors used. It is recommended to use high accuracy resistor of 0.1%. Post Amplifier Error is due to the resistor matching and the voltage offset characteristic which can be found on the supplier datasheet. Isolation Amplifier Error is shown in the table below: Isolation Amplifier Error Calculation Typical 3 s distribution or specification * Fig ACPL-C87AT ACPL-C87BT A Error due to offset voltage (25 °C) 0.015% 0.5% 0.5% Offset Voltage /Recommended input voltage range (2.0 V) specs B Error due to offset voltage drift (across temperature) 0.1% 0.4% 0.4% Offset Voltage /Recommended input voltage range (2.0 V) C Error due to gain tolerance (25 °C) 0% 1% 0.5% specs D Error due to gain drift (across temperature) 0.25% 0.8% 0.8% E Error due to Nonlinearity (across temperature) 0.05% 0.12% 0.12% F Total uncalibrated error (A+B+C+D+E) 0.415% 2.82% 2.32% specs G Total offset calibrated error (F – A) 0.4% 2.32% 1.82% H Total gain and offset calibrated error (G – C) 0.4% 1.32% 1.32% * 3 s distribution is based on corner wafers. |
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