Data Sheet

AD7656A

SOFTWARE SELECTION OF ADCS

The H/S SEL pin determines the source of the combination of

ADCs that are to be simultaneously sampled. When the H/S SEL

pin is logic low, the combination of channels to be simultaneously

sampled is determined by the CONVST A, CONVST B, and

CONVST C pins. When the H/S SEL pin is logic high, the

combination of channels selected for simultaneous sampling is

determined by the contents of the DB15 to DB13 bits in the

control register. In this mode, a write to the control register is

necessary.

The control register is an 8-bit write-only register. Data is

written to this register using the CS and WR pins and the DB15

to DB8 data pins (see Figure 25). The control register is detailed

in Table 8. To select an ADC pair to be simultaneously sampled,

set the corresponding data line high during the write operation.

DATA

DB15 TO DB8

CS

WR

Figure 25. Parallel Interface—Write Cycle for Word Mode (W/B= 0)

The AD7656A control register allows individual ranges to be

programmed on each ADC pair. DB12 to DB10 bits in the

control register are used to program the range on each ADC pair.

After a reset occurs on the AD7656A, the control register

contains all zeros.

The CONVST A signal is used to initiate a simultaneous

conversion on the combination of channels selected via the

control register. The CONVST B and CONVST C signals can be

tied low when operating in software mode (H/S SEL = 1). The

number of read pulses required depends on the number of

ADCs selected in the control register and on whether the

devices are operating in word or byte mode. The conversion

results are output in ascending order.

During the write operation, Data Bus Bit DB15 to Data Bus

Bit DB8 are bidirectional and become inputs to the control

register when RD is logic high and CS and WR are logic low.

The logic state on DB15 through DB8 is latched into the control

register when WR goes logic high.

Table 8. Control Register Bits (Default All 0s)

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

VC

VB

VA

RNGC

RNGB

RNGA

REFEN

REFBUF

Table 9. Control Register Bit Function Descriptions (Default All 0s)

Bit

Mnemonic

Description

DB15

VC

This bit selects the V5 and V6 analog inputs for the next conversion. When this bit is set to 1, V5 and V6 are

simultaneously converted on the next CONVST A rising edge.

DB14

VB

This bit selects the V3 and V4 analog inputs for the next conversion. When this bit is set to 1, V3 and V4 are

simultaneously converted on the next CONVST B rising edge.

DB13

VA

This bit selects the V1 and V2 analog inputs for the next conversion. When this bit is set to 1, V1 and V2 are

simultaneously converted on the next CONVST C rising edge.

DB12

RNGC

DB11

RNGB

DB10

RNGA

DB9

REFEN

This bit selects the internal reference or an external reference. When this bit is set to 0, the external reference mode is

selected. When this bit is set to 1, the internal reference is selected.

DB8

REFBUF

This bit selects between using the internal reference buffers and choosing to bypass these reference buffers. When this

bit is set to 0, the internal reference buffers are enabled and decoupling is required on the REFCAPx pins. When this bit is

set to 1, the internal reference buffers are disabled and a buffered reference is applied to the REFCAPx pins.

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