FEDL9272-02

LAPIS Semiconductor

ML9272

4/15

PIN DESCRIPTION

Symbol

Type

Description

CLK

I

Shift register clock input pin.

Shift register reads data through DIN while the CLK pin is in a low state and the data in

the shift register is shifted from one stage to the next stage at the rising edge of the

clock.

DIN

I

Serial data input pin of the shift register.

Display data (positive logic) is input through the DIN pin in synchronization with clock.

DOUT

O

Serial data output pin of the shift register.

Data is output through the DOUT pin in synchronization with the CLK signal.

When R/L = High, the data of PO40 in the shift register is output through the DOUT pin.

When R/L = Low, the data of PO1 in the shift register is output through the DOUT pin.

LS

I

Latch strobe input pin

When LS is high, the parallel output data (PO1-40) of the shift register read out. When

LS goes from high to low, the parallel output data (PO1-40) of the shift register is held.

CL

I

Clear input pin with a built-in pull-up resistor

The CL pin is normally being set high.

If the CL pin is high and the CHG pin is low, the driver outputs (HV01 to HV40) are in

phase with the corresponding latch outputs (O1 to O40).

If the CL pin is high and the CHG pin is high, the driver outputs (HV01 to HV40) are high

irrespective of the states of the latch outputs.

If the CL pin is set low, the driver outputs are driven low irrespective of the states of the

CHG pin and latch outputs.

This allows display blanking to be set.

CHG

I

Input for testing (with a pull-down resistor)

The CHG pin is normally being set low.

If the CHG pin is low and the CL pin is high, the driver outputs (HV01 to HV40) are in

phase with the corresponding latch outputs (O1 to O40).

If the CHG pin is low and the CL pin is low, the driver outputs (HV01 to HV40) are low

irrespective of the states of the latch outputs.

If the CHG pin is set high and the CL pin is high, the driver outputs are driven high

irrespective of the states of the latch outputs.

This provides the easy testing of all lights after final assembly.

HVO1-40

O

High voltage driver outputs for driving a VFD tube

The driver outputs are in phase with the corresponding latch outputs (O1 to O40).

The direct connection to the grid or anode of a VFD tube eliminates pull-down resistors.



Power supply pin for driver circuits of VFD tube



Power supply pin for logic

D-GND



GND pin for driver circuits of a VFD tube. (D-GND)

Since the D-GND is not connected to L-GND, connect this pin to the external L-GND.

L-GND



GND pin for logic circuits. (L-GND)

Since the L-GND pin is not connected to D-GND, connect this pin to the external

D-GND.

R/L

I

Data shift direction control pin with a built-in pull-up resistor.

When R/L = High, the data shifts from shift register PO1 to shift register PO40.

When R/L = Low, the data shifts from shift register PO40 to shift register PO1.