CS51313 datasheet(15/20 Pages) CHERRY

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where

IRMS(H) = maximum switching MOSFET RMS current;

IL(PEAK) = inductor peak current;

IL(VALLEY) = inductor valley current;

D = Duty Cycle.

Once the RMS current through the switch is known, the

switching MOSFET conduction losses can be calculated:

PRMS(H) = IRMS(H)2 × RDS(ON)

where

PRMS(H) = switching MOSFET conduction losses;

IRMS(H) = maximum switching MOSFET RMS current;

RDS(ON) = FET drain-to-source on-resistance

The upper MOSFET switching losses are caused during

MOSFET switch-on and switch-off and can be determined

by using the following formula:

PSWH = PSWH(ON) + PSWH(OFF)

where

PSWH(ON) = upper MOSFET switch-on losses;

PSWH(OFF) = upper MOSFET switch-off losses;

VIN = input voltage;

IOUT = load current;

tRISE = MOSFET rise time (from FET manufacturer’s

switching characteristics performance curve);

tFALL = MOSFET fall time (from FET manufacturer’s

switching characteristics performance curve);

T = 1/FSW = period.

The total power dissipation in the switching MOSFET can

then be calculated as:

PHFET(TOTAL) = PRMSH + PSWH(ON) + PSWH(OFF),

where

PHFET(TOTAL) = total switching (upper) MOSFET losses;

PRMSH = upper MOSFET switch conduction Losses;

PSWH(ON) = upper MOSFET switch-on losses;

PSWH(OFF) = upper MOSFET switch-off losses.

Once the total power dissipation in the switching FET is

known, the maximum FET switch junction temperature

can be calculated:

TJ = TA + [PHFET(TOTAL) × RθJA],

where

TJ = FET junction temperature;

TA = ambient temperature;

PHFET(TOTAL) = total switching (upper) FET losses;

RθJA = upper FET junction-to-ambient thermal resistance

Step 7b: Selection of the synchronous (lower) FET

The switch conduction losses for the lower FET can be cal-

culated as follows:

PRMSL = IRMS2 × RDS(ON) = [IOUT × (1 − D)]2 × RDS(ON),

where

PRMSL = lower MOSFET conduction losses;

IOUT = load current;

D = Duty Cycle;

RDS(ON) = lower FET drain-to-source on-resistance.

The synchronous MOSFET has no switching losses, except

for losses in the internal body diode, because it turns on

into near zero voltage conditions. The MOSFET body

diode will conduct during the non-overlap time and the

resulting power dissipation (neglecting reverse recovery

losses) can be calculated as follows:

PSWL = VSD × ILOAD × non-overlap time × FSW,

where

PSWL = lower FET switching losses;

VSD = lower FET source-to-drain voltage;

ILOAD = load current

Non-overlap time = GATE(L)-to-GATE(H) or GATE(H)-

to-GATE(L) delay (from CS51313 data sheet Electrical

Characteristics section);

FSW = switching frequency.

The total power dissipation in the synchronous (lower)

MOSFET can then be calculated as:

PLFET(TOTAL) = PRMSL + PSWL,

where

PLFET(TOTAL) = Synchronous (lower) FET total losses;

PRMSL = Switch Conduction Losses;

PSWL = Switching losses.

Once the total power dissipation in the synchronous FET is

known the maximum FET switch junction temperature can

be calculated:

TJ = TA + [PLFET(TOTAL) × RθJA],

where

TJ = MOSFET junction temperature;

TA = ambient temperature;

PLFET(TOTAL) = total synchronous (lower) FET losses;

RθJA = lower FET junction-to-ambient thermal resistance.

Step 8: Control IC Power Dissipation

The power dissipation of the IC varies with the MOSFETs

used, VCC, and the CS51313 operating frequency. The aver-

age MOSFET gate charge current typically dominates the

control IC power dissipation.

The IC power dissipation is determined by the formula:

PCONTROLIC = ICCVCC + PGATE(H) + PGATE(L),

where

PCONTROLIC = control IC power dissipation;

ICC = IC quiescent supply current;

VCC = IC supply voltage;

PGATE(H) = upper MOSFET gate driver (IC) losses;

PGATE(L) = lower MOSFET gate driver (IC) losses.

The upper (switching) MOSFET gate driver (IC) losses are:

PGATE(H) = QGATE(H) × FSW × VGATE(H),

VIN × IOUT × (tRISE + tFALL)

Application Information: continued

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