CS4329 datasheet(22/36 Pages) CIRRUS

22 / 36 page

CDB4329 CDB4390

DS153DB3

CDB4329/90 SYSTEM OVERVIEW

The CDB4329/90 evaluation board is an excellent

means of quickly evaluating the CS4329/90. The

CS8412 digital audio interface receiver provides an

easy interface to digital audio signal sources in-

cluding the majority of digital audio test equip-

ment. The evaluation board also allows the user to

supply clocks and data through a 10-pin header for

system development.

The CDB4329/90 schematic has been partitioned

into 8 schematics shown in Figures 2 through 9.

Each partitioned schematic is represented in the

system diagram shown in Figure 1. Notice that the

system diagram also includes the interconnections

between the partitioned schematics.

CS4329/90 Digital to Analog Converter

A description of the CS4329 or CS4390 is included

in the CS4329 and CS4390 data sheets.

CS8412 Digital Audio Receiver

The system receives and decodes the standard

S/PDIF data format using a CS8412 Digital Audio

Receiver, Figure 9. The outputs of the CS8412 in-

clude a serial bit clock, serial data, left-right clock

(FSYNC), de-emphasis control and a 256Fs master

clock.

During normal operation, the CS8412 operates in

the Channel Status mode where the LED’s display

channel status information for the channel selected

by the CSLR/FCK jumper. This allows the CS8412

to decode and supply the de-emphasis bit from the

digital audio interface for control of the CS4329/90

de-emphasis filter via pin 3, CC/F0, of the CS8412.

When the Error Information Switch is activated,

the CS8412 operates in the Error and Frequency in-

formation mode. The information displayed by the

LED’s can be decoded by consulting the CS8412

data sheet. If the Error Information Switch is acti-

vated, the CC/F0 output has no relation to the de-

emphasis bit and it is likely that the de-emphasis

control for the CS4329/90 will be erroneous and

produce an incorrect audio output.

Encoded sample frequency information can be dis-

played provided a proper clock is being applied to

the FCK pin of the CS8412. When an LED is lit,

this indicates a "1" on the corresponding pin locat-

ed on the CS8412. When an LED is off, this indi-

cates a "0" on the corresponding pin. Neither the L

or R option of CSLR/FCK should be selected if the

FCK pin is being driven by a clock signal.

The evaluation board has been designed such that

the input can be either optical or coax, Figure 8. It

is not necessary to select the active input. However,

both inputs can not be driven simultaneously.

Data Format

The CS4329/90 must be configured to be compati-

ble with the incoming data and can be set with

DIF0, DIF1, and DIF2. The CS8412 data format

can be set with the M0, M1, M2 and M3. There are

several data formats which the CS8412 can pro-

duce that are compatible with CS4329/90. Refer to

Table 2 for one possibility.

Power Supply Circuitry

Power is supplied to the evaluation board by four

binding posts, Figure 10. The +5 Volt input sup-

plies power to the CS4329/90 (through VA+), the

CS8412 (through VA+ and VD+), and the +5 Volt

digital circuitry (through VD+). The ±12 volt input

supplies power to the analog filter circuitry.

Input/Output for Clocks and Data

The evaluation board has been designed to allow

the interface to external systems via the 10-pin

header, J1. This header allows the evaluation board

to accept externally generated clocks and data. The

schematic for the clock/data I/O is shown in Figure

7. The 74HC243 transceiver functions as an I/O

buffer where the CLK SOURCE jumper deter-

mines if the transceiver operates as a transmitter or

receiver.

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