CS4331 datasheet(9/38 Pages) CIRRUS

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Initialization and Power-Down

The Initialization and Power-Down sequence

flow chart is shown in Figure 8. The CS4330/31/33

enter the Power-Down mode upon initial power-

up. The interpolation filters and delta-sigma

modulators are reset, and the internal voltage ref-

erence, one-bit digital-to-analog converters and

switched-capacitor low-pass filters are powered

down. The device will remain in the Power-

Down mode unti l MC LK and LRCK are

presented. Once MCLK and LRCK are detected,

MCLK occurrences are counted over one LRCK

period to determine the MCLK/LRCK frequency

ratio. Power is then applied to the internal volt-

age reference and the +5 or +3 Volt power

supply mode is determined. Finally, power is

applied to the D/A converters and switched-ca-

pacitor filters, and the analog outputs will move

to approximately 2.3V (1.3V in 3V mode). This

process requires approximately 1ms plus 1024

cycles of LRCK.

The CS4330/31/33 enter the Power-Down mode

within 1 period of LRCK if either MCLK or

LRCK is removed. The initialization sequence

begins when MCLK and LRCK are restored. If

the MCLK/LRCK frequency ratio or the VA+

voltage changes during Power-Down, the

CS4330/31/33 adapt to these new operating con-

ditions. It is recomended that the CS4330/31/33

not be powered up with the clocks (MCLK,

LRCK, SCLK) going.

Power Supply Determination

The nominal power supply voltage for the

CS4330/31/33 may be either +5 or +3 Volts.

"SMART Analog" circuitry senses the power

supply voltage during the initialization sequence

or when exiting the Power-Down mode. +5V op-

eration will be set with a 3.7 Vpp full scale

output if VA+ is between 4.75 and 5.5 Volts. The

CS4330/31/33 will be set for +3V operation with

a 1.85 Vpp full scale output if VA+ is between

2.7 and 4.0 Volts. Supply voltages between 4.0

and 4.75 Volts should be avoided to prevent op-

eration in the 5V mode. In this condition there is

insufficient headroom to produce a 3.7 Vpp out-

put.

Grounding and Power Supply Decoupling

As with any high resolution converter, the

CS4330/31/33 require careful attention to power

supply and grounding arrangements to optimize

performance. Figure 1 shows the recommended

power arrangements with VA+ connected to a

clean +3/+5V supply. Decoupling capacitors

should be located as near to the CS4330/31/33

as possible.

Analog Output and Filtering

The CS4330/31/33 analog filter is a switched-ca-

pacitor filter. The switched-capacitor filter

frequency response is clock dependent and will

scale with sample rate.

The digital filter of the CS4330/31/33 is de-

signed to compensate for the magnitude and

phase response of a single-pole low-pass filter at

twice the sample rate. Output filters consisting of

a 2.4 kohm resistor and capacitor are recom-

Gain

-10dB

0dB

Frequency

T2 = 15

T1=50

3.183 kHz

10.61 kHz

Figure 3. De-Emphasis Curve (Fs = 44.1kHz)

CS4330, CS4331, CS4333

DS136F1

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