CS4611 datasheet(15/29 Pages) CIRRUS

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DS241PP5

CS4610/11

CrystalClear™ SoundFusion™ PCI Audio Accelerator

Each digital audio channel is internally buffered

through a 16 sample x 20-bit FIFO. The data format

for the serial digital audio ports varies depending

on the configuration. The primary configurations

supported include a CS4610/11 plus CS423x con-

figuration for motherboard audio, a CS4610/11

plus CS423x configuration with full 5.1 channel

output capability, and an AC’97 controller config-

uration (CS4610/11 plus an AC’97 Codec).

CS4610/11 + CS423x Motherboard Audio

Accelerator

A system block diagram for the CS4610/11 plus

CS423x configuration is given in Figure 6. This

configuration utilizes a proprietary bi-directional

digital audio link between the CS4610/11 and the

CS423x. The connection between these devices is

depicted in Figure 9.

In the CS4610/11 plus CS423x configuration, the

CS423x is the serial port timing master. The serial

port runs at a fixed 44.1 kHz sampling rate, and the

2.822 MHz SCLK output from the CS423x is selected

as the CS4610/11 PLL clock generator input.

Note that in this configuration the SDIN signal car-

ries two stereo streams from the CS423x to the

CS4610/11: the CS423x ADC data and the CS423x

output data. The SDOUT signal carries the

CS4610/11 final output to the CS423x DACs.

SDIN and SDOUT transitions occur on rising edg-

es of SCLK (SDIN is sampled on falling edges of

SCLK). The data is transmitted in left-justified for-

mat, MSB first, 16-bit data, with 32 clock cycles

for each phase of the FSYNC signal. FSYNC tran-

sitions occur on rising edges of SCLK, the FSYNC

high phase indicates left channel data on SDIN and

SDOUT while the FSYNC low phase indicates

right channel data. The SDOUT signal carries 16

bits of data followed by 16 bits of zero pad for each

channel (left and right). The SDIN signal carries 16

bits of ADC data followed by 16 bits of playback

data for each channel (left and right). The serial

port clock and data timing relationship for this con-

figuration is indicated in Figure 10. The clock and

data signal functions for this configuration are

summarized in Table 3.

Motherboard Configuration with 5.1 channel

output capability (CS4610 only)

This configuration is the same as the CS4610 plus

CS423x motherboard accelerator configuration

with the addition of two Crystal™ CS4333 Stereo

CS4610/11 PCI

Accelerator

CS423x

ISA Codec

64Fs (2.822 MHz)

44.1 kHz (fixed)

ABITCLK/SCLK

ASYNC/FSYNC

ASDOUT/SDOUT

MIDIIN

ASDIN/SDIN

SCLK

FSYNC

SDIN

MIDOUT

SDOUT

16.9344 MHz

PLL/

Clock Gen

Figure 9. CS4610/11 + CS423x Connection Diagram

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