CS5320/21/22

14

DS454PP1

Notes: 24. If MCLK is removed, the modulator will enter the power down mode.

25. Excludes MCLK input. MCLK should be driven with a signal having rise and fall times of 25 ns or faster.

26. Only the rising edge of MSYNC relative to MCLK is used to synchronize the device. MSYNC can return

low at any time as long as it remains high for at least one MCLK cycle.

Parameter

Symbol

Min

Typ

Max

Units

MCLK Frequency

(Note 24)

0.512

1.024

1.1

MHz

MCLK Duty Cycle

40

-

60

%

Rise Times:

Any Digital Input

(Note 25)

Any Digital Output

-

-

-

50

100

200

ns

ns

Fall Times:

Any Digital Input

(Note 25)

Any Digital Output

-

-

-

50

100

200

ns

ns

SYNC Setup Time to CLKIN rising

20

-

-

ns

SYNC Hold Time after CLKIN rising

20

-

-

ns

CLKIN edge to MCLK edge

-30

-

ns

MCLK rising to Valid MDATA

-50

-

ns

MSYNC Delay from MCLK rising

(Note 26)

-90

-

ns

CLKIN

SYNC

LSYNC*

MCLK

MSYNC

MDATA

MFLG

* Internal timing signal generated in the CS5322

FILTER

SAMPLES

DATA

VALID DATA

VALID DATA

Figure 17. CS5320/21/CS5322 Interface Timing