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CS5351 Datasheet(PDF) 18 Page - Cirrus Logic

Part # CS5351
Description  108 dB, 192 kHz, Multi-Bit Audio A/D Converter
PDF  24 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS5351 Datasheet(HTML) 18 Page - Cirrus Logic

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CS5351
18
DS565PP2
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT (Logic "0" = GND = 0 V;
Logic "1" = VL = 2.37V to 5.25V, VA = 5V
±5%, VD = 3.1V to 5.25V, C
L =20pF)
Parameter
Symbol
Min
Typ
Max
Unit
Input Sample Rate
Single Speed Mode
Double Speed Mode
Quad Speed Mode
Fs
Fs
Fs
2
50
100
-
-
-
50
100
192
kHz
kHz
kHz
OVFL to LRCK edge setup time
tsetup
16/fsclk
--
s
OVFL to LRCK edge hold time
thold
1/fsclk
--
s
OVFL time-out on overrange condition
Fs = 44.1, 88.2, 176.4kHz
Fs = 48, 96, 192kHz
-
-
740
680
-
-
ms
ms
MCLK Specifications
MCLK Period
tclkw
40
-
1953
ns
MCLK Pulse Width High
tclkh
15
-
-
ns
MCLK Pulse Width Low
tclkl
15
-
-
ns
Master Mode
SCLK falling to LRCK
tmslr
-20
-
20
ns
SCLK falling to SDOUT valid
tsdo
0
-
40
ns
SCLK Duty Cycle
-
50
-
%
SCLK Output Frequency
-
50
-
%
Slave Mode
Single Speed
Output Sample Rate
Fs
2
-
50
kHz
LRCK Duty Cycle
405060
%
SCLK Period
tsclkw
163
-
-
ns
SCLK High/Low
tsclkhl
20
-
-
ns
SCLK falling to SDOUT valid
tdss
-
-
40
ns
SCLK falling to LRCK edge
tslrd
-20
-
20
ns
Double Speed
Output Sample Rate
Fs
50
-
100
kHz
LRCK Duty Cycle
405060
%
SCLK Period
tsclkw
163
-
-
ns
SCLK High/Low
tsclkhl
20
-
-
ns
SCLK falling to SDOUT valid
tdss
-
-
40
ns
SCLK falling to LRCK edge
tslrd
-20
-
20
ns
Quad Speed
Output Sample Rate
Fs
100
-
192
kHz
LRCK Duty Cycle
405060
%
SCLK Period
tsclkw
81
-
-
ns
SCLK High/Low
tsclkhl
20
-
-
ns
SCLK falling to SDOUT valid
tdss
-
-
20
ns
SCLK falling to LRCK edge
tslrd
-10
-
10
ns



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