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W166
6
Application Information
Recommended Circuit Configuration
For optimum performance in system applications the power
supply decoupling scheme shown in Figure 4 should be used.
VDD decoupling is important to both reduce phase jitter and
EMI radiation. The 0.1-
µF decoupling capacitor should be
placed as close to the VDD pin as possible, otherwise the in-
creased trace inductance will negate its decoupling capability.
The 10-
µF decoupling capacitor shown should be a tantalum
type. For further EMI protection, the VDD connection can be
made via a ferrite bead, as shown.
Recommended Board Layout
Figure 5 shows a recommended a 2-layer board layout.
Document: #38-00878
Figure 4. Recommended Circuit Configuration
GND
8
7
6
5
1
2
3
4
C1
FB
C2
3.3 or 5V System Supply
10 µF Tantalum
VDD
0.1 µF
Clock Output
Reference Input
NC
R1
Ordering Information
Ordering Code
Package
Name
Package Type
W166
G
8-pin Plastic SOIC (150-mil)
Figure 5. Recommended Board Layout (2-Layer Board)
Clock Output
High frequency supply decoupling
capacitor (0.1 µF recommended).
Common supply low frequency
decoupling capacitor (10-µF tantalum
recommended).
FB
Ferrite Bead
C1 =
C2 =
Match value to line impedance
R1 =
=
R1
C1
C2
G
G
FB
=
Via To GND Plane
G
Reference Input
NC
G
Power Supply Input
(3.3V or 5V)
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