Six Output Peak Reducing EMI Solution
W184
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
July 25, 2000, rev. *B
Features
• Cypress PREMIS™ family offering
• Generates an EMI optimized clocking signal at the
output
• Selectable input to output frequency
• Six 1.25%, 3.75%, or 0% down or center spread outputs
• One non-Spread reference output
• Integrated loop filter components
• Operates with a 3.3 or 5V supply
• Low power CMOS design
• Available in 24-pin SSOP (Shrunk Small Outline
Package)
• Outputs may be selectively disabled
Key Specifications
Supply Voltages: ........................................... VDD = 3.3V±5%
or VDD = 5V±10%
Frequency Range: .............................. 8 MHz
≤ F
in ≤ 28 MHz
Crystal Reference Range.................... 8 MHz
≤ F
in ≤ 28 MHz
Cycle to Cycle Jitter: ........................................ 300 ps (max.)
Selectable Spread Percentage: ....................1.25% or 3.75%
Output Duty Cycle: ............................... 40/60% (worst case)
Output Rise and Fall Time: .................................. 5 ns (max.)
Table 1. Modulation Width Selection
SS%
W184
Output
W184-5
Output
0Fin ≥ Fout ≥ Fin – 1.25%
Fin + 0.625% ≥ Fin≥ –
0.625%
1Fin ≥ Fout ≥ Fin – 3.75%
Fin + 1.875% ≥ Fin≥
–1.875%
Table 2. Frequency Range Selection
FS2
FS1
Frequency Range
00
8 MHz
≤ F
IN ≤ 10 MHz
0
1
10 MHz
≤ F
IN ≤ 15 MHz
10
15 MHz
≤ F
IN ≤ 18 MHz
11
18 MHz
≤ F
IN ≤ 28 MHz
Table 3. Output Enable
EN1
EN2
CLK0:4
CLK5
0
0
Low
Low
01
Low
Active
10
Active
Low
1
1
Active
Active
PREMIS is a trademark of Cypress Semiconductor Corporation.
Simplified Block Diagram
Pin Configuration
Spread Spectrum
W184
(EMI suppressed)
3.3 or 5.0V
Oscillator or
Spread Spectrum
W184
(EMI suppressed)
3.3 or 5.0V
XTAL
X1
X2
Reference Input
Input
Outputs
Outputs
24
23
22
21
1
2
3
4
REFOUT
FS2
X1
X2
SSON#
RESET
FS1
VDD
5
6
7
18
19
20
VDD
NC
EN1
GND
SS%
EN2
8
9
10
15
16
17
CLK5
VDD
CLK4
GND
CLK0
VDD
13
14
GND
CLK3
11
12
CLK1
CLK2
SSOP
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