Spread Spectrum FTG for 440BX and VIA Apollo Pro-133
W196
PRELIMINARY
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
October 28, 1999, rev. **
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum Technology
• System frequency synthesizer for 440BX, 440ZX, and
VIA Apollo Pro-133
•I2C programmable to 155 MHz (32 selectable
frequencies)
• Two skew-controlled copies of CPU output
• Seven copies of PCI output (synchronous w/CPU out-
put)
• One copy of 14.31818-MHz IOAPIC output
• One copy of 48-MHz USB output
• Selectable 24-/48-MHz clock is determined by resistor
straps on power up
• One high-drive output buffer that produces a copy of
the 14.318-MHz reference
• Isolated core VDD pin for noise reduction
Key Specifications
Supply Voltages: ....................................... VDDQ3 = 3.3V±5%
VDDQ2 = 2.5V±5%
CPU Cycle to Cycle Jitter: .......................................... 250 ps
CPU, PCI Output Edge Rate:
.........................................≥1 V/ns
CPU0:1 Output Skew: ................................................ 175 ps
PCI_F, PCI1:6 Output Skew: .......................................500 ps
CPU to PCI Skew: ........................ 1.5 to 4.0 ns (CPU Leads)
REF2X/SEL48#, SCLOCK, SDATA: ............... 250-k
Ω pull-up
FS1: ............................................................250-k
Ω pull-down
FS0: ...................................................No pull-up or pull-down
Note: Internal pull-up or pull-down resistors should not be re-
lied upon for setting I/O pins HIGH or LOW.
Table 1. Pin Selectable Frequency
FS1
FS0
CPU(0:1)
PCI
1
1
133.3 MHz
33.3 MHz
1
0
105 MHz
35 MHz
0
1
100 MHz
33.3 MHz
0
0
66.8 MHz
33.3 MHz
Pin Configuration
Block Diagram
X1
X2
GND
PCI_F
PCI1
PCI2
PCI3
PCI4
VDDQ3
PCI5
PCI6
VDDQ3
48MHz
24_48MHz/FS1
GND
REF2X/SEL48#
VDDQ3
VDDQ2
IOAPIC
VDDQ2
CPU0
CPU1
VDDQ3
GND
SDATA
SCLOCK
FS0
GND
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VDDQ3
REF2X/SEL48#
VDDQ3
IOAPIC
CPU0
CPU1
PCI_F
XTAL
PLL Ref Freq
PLL 1
FS1
X2
X1
VDDQ3
PCI1
PCI2
PCI3
PCI4
PCI5
48MHz
24_48MHz/FS1
PLL2
÷2/÷3
OSC
VDDQ2
PCI6
GND
GND
VDDQ3
GND
GND
I2C
SCLOCK
SDATA
LOGIC
FS0
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