DS1232LP/LPS

Low Power MicroMonitor Chip

DS1232LP/LPS

062698 1/7

FEATURES

failure

monitoring

age available

ignated N

PIN ASSIGNMENT

1

2

3

4

8

7

6

5

ST

RST

RST

PBRST

TD

TOL

GND

DS1232LP 8–Pin DIP

(300 Mil)

See Mech. Drawings

Section

DS1232LPS 16–Pin SOIC

(300 Mil)

See Mech. Drawings

Section

1

2

3

4

5

6

7

8

TD

TOL

GND

PBRST

VCC

ST

RST

RST

DS1232LPS–2 8–Pin

SOIC

(150 Mil)

See Mech. Drawings

Section

NC

PBRST

NC

TD

NC

TOL

NC

GND

NC

VCC

NC

ST

NC

RST

NC

RST

1

11

12

13

14

2

3

4

5

6

7

8

9

10

15

16

DS1232LP

µ

(118 MIL

µ–SOP)

See Mech. Drawings

Section

ST

RST

RST

8

7

6

5

1

2

3

4

PBRST

TD

TOL

GND

PIN DESCRIPTION

PBRST

– Pushbutton Reset Input

TD

– Time Delay Set

TOL

GND

– Ground

RST

– Reset Output (Active High)

RST

– Reset Output (Active Low, open drain)

ST

– Strobe Input

– +5 Volt Power

DESCRIPTION

The DS1232LP/LPS Low Power MicroMonitor Chip

monitors three vital conditions for a microprocessor:

power supply, software execution, and external over-

ride. First, a precision temperature–compensated refer-

When an out–of–tolerance condition occurs, an internal

power fail signal is generated which forces reset to the

tion, the reset signals are kept in the active state for a

minimum of 250 ms to allow the power supply and pro-

cessor to stabilize.

The second function the DS1232LP/LPS performs is

pushbutton reset control. The DS1232LP/LPS de-

bounces the pushbutton input and guarantees an active

reset pulse width of 250 ms minimum. The third function

is a watchdog timer. The DS1232LP/LPS has an inter-

nal timer that forces the reset signals to the active state if