DS1315

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TIMING BLOCK DIAGRAM Figure 1

Communication with the Time Chip is established by pattern recognition of a serial bit stream of 64 bits

which must be matched by executing 64 consecutive write cycles containing the proper data on data in

(D). All accesses which occur prior to recognition of the 64-bit pattern are directed to memory via the

After recognition is established, the next 64 read or write cycles either extract or update data in the Time

Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control

CEI

When the first write cycle is executed, it is compared to bit 1 of the 64-bit comparison register. If a match

is found, the pointer increments to the next location of the comparison register and awaits the next write

cycle. If a match is not found, the pointer does not advance and all subsequent write cycles are ignored. If

a read cycle occurs at any time during pattern recognition, the present sequence is aborted and the

comparison register pointer is reset. Pattern recognition continues for a total of 64 write cycles as

described above until all the bits in the comparison register have been matched. (This bit pattern is shown

in Figure 2). With a correct match for 64 bits, the Time Chip is enabled and data transfer to or from the

timekeeping registers may proceed. The next 64 cycles will cause the Time Chip to either receive data on