DS9034PCX datasheet(3/20 Pages) DALLAS

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DS1386/1386P

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PACKAGES

The DS1386 is available in two packages (32-pin DIP module and 34-pin PowerCap module). The 32-pin

DIP style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin

PowerCap Module Board is designed with contacts for connection to a separate PowerCap (DS9034PCX)

that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the

DS1386P after the completion of the surface mount process. Mounting the PowerCap after the surface

mount process prevents damage to the crystal and battery due to high temperatures required for solder

reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap

are ordered separately and shipped in separate containers. The part number for the PowerCap is

DS9034PCX.

OPERATION - READ REGISTERS

The DS1386 executes a read cycle whenever WE (Write Enable) is inactive (High), CE (Chip Enable)

and OE (Output Enable) are active (Low). The unique address specified by the address inputs (A0-A14)

defines which of the registers is to be accessed. Valid data will be available to the eight data output

drivers within tACC (Access Time) after the last address-input signal is stable, providing that CE and OE

access times are also satisfied. If OE and CE access times are not satisfied, then data access must be

measured from the latter occurring signal ( CE or OE ) and the limiting parameter is either tCO for CE or

tOE for OE rather than address access.

OPERATION - WRITE REGISTERS

The DS1386 is in the write mode whenever the WE (Write Enable) and CE (Chip Enable) signals are in

the active (Low) state after the address inputs are stable. The latter occurring falling edge of CE or WE

will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE

or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state

for a minimum recovery state (tWR) before another cycle can be initiated. Data must be valid on the data

bus with sufficient Data Set-Up (tDS) and Data Hold Time (tDH) with respect to the earlier rising edge of

or WE . The OE control signal should be kept inactive (High) during write cycles to avoid bus

contention. However, if the output bus has been enabled ( CE and OE active), then WE will disable the

outputs in tODW from its falling edge.

DATA RETENTION

The RAMified Timekeeper provides full functional capability when VCC is greater than 4.5 volts and

write-protects the register contents at 4.25 volts typical. Data is maintained in the absence of VCC without

any additional support circuitry. The DS1386 constantly monitors VCC. Should the supply voltage decay,

the RAMified Timekeeper will automatically write-protect itself and all inputs to the registers become

“don’t care.” The two interrupts INTA and INTB (INTB) and the internal clock and timers continue to run

regardless of the level of VCC. However, it is important to insure that the pull-up resistors used with the

interrupt pins are never pulled up to a value that is greater than VCC + 0.3V. As VCC falls below

approximately 3.0 volts, a power switching circuit turns the internal lithium energy source on to maintain

the clock and timer data and functionality. It is also required to insure that during this time (battery

backup mode), the voltage present at INTA and INTB (INTB) never exceeds 3.0V. During power-up,

when VCC rises above approximately 3.0 volts, the power switching circuit connects external VCC and

disconnects the internal lithium energy source. Normal operation can resume after VCC exceeds 4.5 volts

for a period of 200 ms.

DS9034PCX Datasheet(PDF) 3 Page - Dallas Semiconductor

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